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System-level vulnerability estimation for data caches

Haghdoost, A ; Sharif University of Technology | 2010

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  1. Type of Document: Article
  2. DOI: 10.1109/PRDC.2010.9
  3. Publisher: 2010
  4. Abstract:
  5. Over the past few years, radiation-induced transient errors, also referred to as soft errors, have been a severe threat to the data integrity of high-end and mainstream processors. Recent studies show that cache memories are among the most vulnerable components to soft errors within high-performance processors. Accurate modeling of the Vulnerability Factor (VF) is an essential step towards developing cost-effective protection techniques for cache memory. Although Fault Injection (FI) techniques can provide relatively accurate VF estimations they are often very time consuming. To overcome the limitation, recent analytical models were proposed to compute the cache VF in a timely fashion. In this paper, we extend previous work and propose an alternative analytical model to compute System-level Vulnerability Factor (SVF) for both write-through and write-back data caches. In our proposed analytical model, we take into account both read frequency and error masking to compute systemlevel vulnerability of data cache. Previously suggested modeling techniques overlook the issues of read frequency and error masking, mainly focusing on time periods in which an error could propagate in the system. In this work we show that overlooking these two parameters can significantly impact the system-level VFs for data caches. We report our estimations for SPEC'2K benchmarks and compare to previously suggested models. Our experimental results show that the proposed modeling technique changes previous VF estimations by up to 40%
  6. Keywords:
  7. System level vulnerability estimation ; Accurate modeling ; Analytical model ; Architectural vulnerability factor ; Cost-effective protection ; Data caches ; Data integrity ; Error masking ; Fault injection ; High performance processors ; Modeling technique ; Radiation-induced ; Soft error ; System levels ; Time-periods ; Transient errors ; Two parameter ; Write-back ; Computer simulation ; Errors ; Estimation ; Mathematical models ; Models ; Cache memory
  8. Source: 16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010, Tokyo, 13 December 2010 through 15 December 2010 ; 2010 , Pages 157-164 ; 9780769542898 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/5703240