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Exploiting Imprecise Non-volatile Memories for Soft Real-time Embedded Systems to Achieve Low Energy Consumption

Bahrami, Fahimeh | 2016

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 48869 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Ejlali, Alireza
  7. Abstract:
  8. Spin-Transfer-Torque-RAM (STT-RAM) has recently been widely accepted as a promising replacement for SRAM technology through the technology scaling due to its high density, zero standby power and comparable-to-SRAM read access latency. However, there are two major obstacles to use STT-RAM, namely, high write access latency and energy. In this study, we propose two approaches to solve these challenges in embedded systems. The conventional latency of the STT-RAM write operation is 10ns and lowering the write latency causes the required write current exponentially increase, leading to a larger memory cell area and a shorter memory lifetime. As the first proposed method, we have assessed the inter-relationship among the write time, the write current and the probability of successful write. We have observed that increasing the write current to reduce the write pulse width to below 10 ns, with tolerance small probabilities of write failures is possible. We leverage this observation to propose a method for determining the write current and the write time for approximable store instructions in a way that significantly reduce the write latency. Our method improves the average memory access latency of the applications and system energy by %50.5 and %22.3, respectively, with a negligible (%2.2) overhead on the memory access energy. As the second proposed method, we identify and characterize a new opportunity for approximate storage in STT-RAM memory that offers energy benefits at the cost of small prob abilities of retention failure. We design an STT-RAM-based multi-retention approximate memory that uses this mechanism, making it feasible for scratchpad memory in embedded systems. A novel multi-retention partitioning, based on required quality levels, is proposed, featuring multiple storage regions with different energy, performance, and quality characteristics. The experimental results show that the proposed method can reduce the memory energy consumption and access latency by %38/3 and %32/7, respectively
  9. Keywords:
  10. Energy Consumption Reduction ; Nonvolatile Memory ; Low Latency ; Spin Transfer Torque-Magnetic (STT-MRAM) ; Imprecise Memories ; Reduce Access Latency

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