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Fault Rate Modeling in Terms of Power Consumption and Thermal Variation in Optical Networks-on-Chip

Abolhasani Zeraatkar, Alireza | 2016

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 49209 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Koohi, Somayyeh
  7. Abstract:
  8. Global on chip communication becomes a critical power bottleneck in high performance many core architectures. The importance of power dissipation in networks-on-chip along with power reduction capability of on-chip nanophotonic interconnects has made optical network on chip a novel technology. Major advantages like high bandwidth, light speed latency and low power consumption, provide a promising solution for future of communications in many core architectures. However, the basic elements that are embedded in optical networks on chip are extremely temperature sensitive. This would lead to change in the physical characteristics of nanophotonic elements which may cause failure in network on chip reliable operation. In this thesis, we have extracted a model of reliability for two different optical network on chip topologies against thermal fluctuations, also we have employed the modifiability of light source power in order to improve the reliability of optical networks on chip. Analytical models of λ-router is proposed with respect to signal-to-noise ratio and bit error rate measurements. In addition, statistical model is obtained using the network simulator OMNeT++. Results show that by using the proposed method, we have gained 39%, 33% and 30% improvement on reliability in 16, 36 and 64 core networks, respectively. Low overhead of proposed method in comparison with traditional networks makes it an appropriate choice for deployment in optical networks on chip
  9. Keywords:
  10. Reliability ; Modeling ; Power Consumption ; On-Chip Optical Network ; Temperature Variation

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