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Designing low power and durable digital blocks using shadow nanoelectromechanical relays

Yazdanshenas, S ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/TVLSI.2016.2553106
  3. Publisher: Institute of Electrical and Electronics Engineers Inc
  4. Abstract:
  5. Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM relays have been significantly investigated as highly energy-efficient design solutions. A major shortcoming of NEMs preventing their widespread use is their limited switching endurance. Hence, in order to utilize the low-power advantages of NEM relays, further device, circuit, and architectural techniques are required. In this paper, we introduce the concept of shadow NEM relays, which is a circuit-level technique to leverage the energy efficiency of the NEM relays despite their low switching endurance. This technique creates two virtual ground nodes in a block to allow: 1) a low power mode with functional NEM relays and 2) a normal mode with failed NEM relays. To demonstrate the applicability of this concept, we have applied it to a six-transistor SRAM cell as an illustrative example. We also investigate the applicability of this SRAM cell in field-programmable gate arrays and on-chip caches. Experimental results reveal that shadow NEM relays can reduce the power consumption of SRAM cells by up to 80% while addressing the limited switching endurance of NEM relays
  6. Keywords:
  7. Nanoelectromechanical (NEM) relays ; On-chip memory ; Shadow logic ; Static random access memory ; Switching endurance ; Durability ; Energy efficiency ; Field effect transistors ; Field programmable gate arrays (FPGA) ; Integrated circuit design ; Low power electronics ; Metals ; MOS devices ; Oxide semiconductors ; Reconfigurable hardware ; Static random access storage ; Circuit levels ; Complementary metal oxide semiconductors ; Digital blocks ; Emerging technologies ; Energy-efficient design ; Low power modes ; Nano-electromechanical ; On-chip cache ; Semiconductor relays
  8. Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 24, Issue 12 , 2016 , Pages 3489-3498 ; 10638210 (ISSN)
  9. URL: http://ieeexplore.ieee.org/document/7463024