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Investigation of the Effect of Interleaved Memory on WCET in Real-Time Embedded System

Hossein Ghorban, Ali | 2017

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 50055 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Ejlali, Alireza
  7. Abstract:
  8. Worst case execution time (WCET) and energy consumption are two of the most important design constraints of real-time embedded systems and memory subsystem has a major impact on both of them. Therefore, many recent studies have tried to improve the memory subsystem of embedded systems by using emerging non-volatile memories instead of conventional memories such as SRAM and DRAM. Indeed, the low leakage power dissipation and improved density of emerging non-volatile memories, makes them prime candidates for replacing the conventional memories. However, accessing these memories imposes performance and energy overhead and using them as the code memory may increase the WCET.Furthermore, most previous studies that have tried to address such problems have focused on the data memory and therefore are not suitable for the code memory. In this paper, we propose a new code memory architecture for non-volatile memories which reduces the effective memory access latency by employing memory access interleaving technique. The proposed architecture can achieve improved WCET and performance with minimum energy consumption overhead. The proposed architecture is evaluated using different benchmark suites and the results show that compared to previous studies, the proposed architecture can improve the WCET and average case execution time of the system by 27% and 55% respectively with 18% memory energy consumption overhead
  9. Keywords:
  10. Nonvolatile Memory ; Memory Management ; Embedded Real-Time System ; Worst-Case Execution Time (WCET) ; Energy Consumption

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