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A novel SET/SEU hardened parallel I/O port

Razmkhah, M. H ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1109/CAS-ICTD.2009.4960762
  3. Publisher: 2009
  4. Abstract:
  5. The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event transient SET and single event upset SEU, caused by energetic particles striking system wires and flip flops. This paper presents a novel SET/SEU-detection technique for I/O ports where different sampling times used to detect the effects of SET/SEUs. The power dissipation, area, reliability, and propagation delay of the SET/SEU-detection I/O port are analyzed by HSPICE v.X-2005.v9 simulation. The results show that this I/O port can detect all SET/SEUs, by consumption of about 113% more power and occupation of 145% more area than simple I/O port. ©2009 IEEE
  6. Keywords:
  7. Fault tolerance ; I/O port ; MEU ; SET/SEU ; CMOS technology ; Detection technique ; Energetic particles ; Feature sizes ; I/O port ; I/O ports ; MEU ; Parallel I/O ; Power dissipation ; Propagation delays ; SET/SEU ; Single event transients ; Single event upsets ; CMOS integrated circuits ; Fault tolerance ; Fault tolerant computer systems ; Quality assurance ; Transients ; Ports and harbors
  8. Source: 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09, Chengdu, 28 April 2009 through 29 April 2009 ; 2009 ; 9781424425877 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4960762