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Design of a High Speed Time-Interleaved SAR ADC

Ghajari, Shahaboddin | 2017

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 50159 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sharifkhani, Mohammad; Fotowat Ahmadi, Ali
  7. Abstract:
  8. The digital nature of Successive Approximation Register (SAR) Analog to Digital Converter (ADC) suits them for the new technologies with small gate length and low power applications. Applications such as ultra-wideband receivers, satellite receivers and high speed serial links demand medium resolution and high sampling rate ADCs. Due to binary search algorithm speed limitations, SAR ADCs belong to low to moderate speed category. In this thesis time-interleaving and two-bit-per-cycle technique are used in order to increase SAR ADC sampling rate. These techniques are both sensitive to offset and if the comparators used in SAR ADC have different offsets signal-to-noise-and-distortion will be affected. In this thesis a new method to calibrate comparator’s offset used in 2-bit per cycle SAR ADC is proposed that not only cancels the offset between comparators but also cancels the offset between sub-ADCs. With the aid of the proposed method a 1 GS/s 6-bit 2b/cycle SAR ADC is designed in 65nm CMOS TSMC. The ADC consumes 3.34 mW from a 1.2 V supply and achieved signal-to-noise-and-distortion of 37.52 dB, spurious-free-dynamic-range of 53.47 dB, effective-resolution-bandwidth of 3.2 GHz with RC model of the input buffer and figure of merit of 54.73 fJ/Conv.Step at Nyquist frequency input. The FoM with mean SNDR derived from Monte-Carlo simulation is 60.42 fJ/Conv.Step
  9. Keywords:
  10. Successive Approximation Register (SAR) ; Analog to Digital Converter ; Time Interleaved Converter ; Monte Carlo Simulation ; 2-Bit Per Cycle ; Offset Calibrations

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