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Bias temperature instability mitigation via adaptive cache size management

Rohbani, N ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/TVLSI.2016.2606579
  3. Abstract:
  4. Bias temperature instability (BTI) is one of the major CMOS reliability issues in nanoscales. The main impact of BTI on SRAM memory cells is the degradation of the static noise margin (SNM), which leads to a higher susceptibility to failures. A variety of techniques for mitigating the impact of BTI on caches have been proposed at architecture level. However, their considerable overheads limit the application of such techniques. Recent studies showed that the utilization of the cache capacity widely varies from one workload to another and even within a workload. When cache utilization is low, for the majority of the cells, the same value is stored for a very long period, which significantly degrades SNM due to BTI. In this paper, we propose a technique to dynamically adjust the cache size according to the running workload cache requirement by monitoring the cache miss rate. The unused cache capacity is power gated to increase the energy efficiency and mitigate aging of the entire cache. The experimental results show that the proposed technique reduces hold and read SNM degradation by up to 48.1% and 33.3%, respectively, at the cost of 2.0% performance penalty. © 2016 IEEE
  5. Keywords:
  6. Aging ; Bias temperature instability (BTI) ; Cache memory ; Static noise margin (SNM) ; Energy efficiency ; Bias temperature instability ; Cache capacity ; Cache miss rates ; Cache utilization ; CMOS reliability ; Performance penalties ; SRAM memory cells ; Static noise margin ; Static random access storage
  7. Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 25, Issue 3 , 2017 , Pages 1012-1022 ; 10638210 (ISSN)
  8. URL: https://ieeexplore.ieee.org/document/7572908