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Design and optimization of reliable hardware accelerators: leveraging the advantages of high-level synthesis

Naz Taher, F ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/IOLTS.2018.8474222
  3. Abstract:
  4. This work proposes an automatic method to generate opti- mized redundant hardware accelerator with maximum reliabil- ity given a single behavioral description for High-Level Syn- thesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over traditional RT- level design: The ability to generate micro-architectures with unique characteristics from the same behavioral description. This is typically done by setting different synthesis options to determine how to synthesize loops, arrays and functions and to specify the number and type of Functional Units (FUs) to be instantiated. The proposed method is composed of two main phases. The first phase performs HLS Design Space Exploration (DSE) leading to a trade-off curve of designs with a unique area, execution time and reliability. The second phase finds the most reliable system given an area and time constraint by either implementing time or space redundancy, or a mixture of both using any combinations of micro-architectures found by the explorer. This second phase has been formulated as an integer linear program (ILP). Experimental results show that the proposed method provides a 20% reliability increase compared to the most common approach of simply using a single micro-architecture and instantiating it multiple times with no significant area or timing overhead. © 2018 IEEE
  5. Keywords:
  6. Architecture ; Economic and social effects ; Hardware ; High level synthesis ; Integer programming ; Systems analysis ; Behavioral descriptions ; Design and optimization ; Design space exploration ; Hardware accelerators ; Integer linear programs ; Micro architectures ; Synthesis options ; Time constraints ; Computer architecture
  7. Source: 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018, 2 July 2018 through 4 July 2018 ; 2018 , Pages 232-235 ; 9781538659922 (ISBN)
  8. URL: https://ieeexplore.ieee.org/document/8474222