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Designing Instruction Prefetcher with Low Area Overhead for Server Workloads

Faghih, Faezeh | 2019

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 51608 (19)
  4. University: Sharif University of Technology
  5. Department: computer engineering
  6. Advisor(s): Sarbazi Azad, Hamid; Lotfi Kamran, Pejman
  7. Abstract:
  8. L1 instruction cache misses creates a crucial performance bottleneck for server applications. Server applications extensively use operating system services, and as such, have large instruction footprint that dwarfs instruction cache size. Meanwhile, fast access requirements preclude enlarging instruction cache that can hold the whole instruction footprint of current server workloads. Prior works proposed using hardware prefetching schemes to eliminate or reduce the effect of instruction cache misses. They use the fact that server application instruction sequences are repetitive. So by recording and prefetching based on such sequesnces, L1 insruction misses could be reduced. While they are effective at reducing front-end stalls and boosting the performance, they require high storage overheads, making them challenging for being implemented in current processors. In this work, we tackle the high overhead of such methods and propose a new instruction prefetching scheme. Our method burdens minimal hardware overhead while preserving the performance improvement of prior works. Cuckoo Discontinuity Prefetcher (CDIP) imposes less than 1/15 of the state-of-the-art prefetcher's area, while the average performance improvement of the CDIP and the state-of-the-art prefethcer is 12 percent and 14 percent respectively
  9. Keywords:
  10. Prefetching ; Overhead Reduction ; Miss Penalty Reduction ; Server Processors

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