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Integrated output matching networks for class-J/J-1 power amplifiers

Alizadeh, A ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSI.2019.2912007
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. In this paper, two output matching networks (OMNs) are proposed for integrated class-J and class-J-1 mode power amplifiers (PAs). The first MN provides the required load impedances of the class-J mode (i.e., Z(f0) = Ropt + j Ropt and Z(2 f0) = -j (3π/8)Ropt), where as the second MN realizes the optimal impedances of class-J-1 PAs (i.e., Z(f0) = Ropt - j Ropt and Z(2 f0) = j (3π/8)Ropt ). Detailed theoretical analyses are presented for each MN, and the values of matching components (i.e., inductors and capacitors) are obtained in terms of Ropt. Analytical derivations are verified by simulation results, while bandwidth and loss performances of each MN are also characterized. Two proof-of-concept class-J and class-J-1 PAs are designed and implemented in a 0.25-μm GaAs process, where the proposed OMNs are employed in the designed circuits. The manufactured PAs show ≥28 dBm output power, ≥65% drain efficiency, and ≥61% power-added efficiency at 2 GHz. © 2019 IEEE
  6. Keywords:
  7. Class-J power amplifier ; Class-J-1 power amplifier ; High-efficiency power amplifiers ; Power amplifiers ; Standard matching networks ; Efficiency ; Gallium arsenide ; III-V semiconductors ; Class J ; High efficiency power amplifiers ; Loss performance ; Matching networks ; Output matching network ; Power amplifiers (PAs) ; Power-added efficiency ; Proof of concept
  8. Source: IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 66, Issue 8 , 2019 , Pages 2921-2934 ; 15498328 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8705659