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Estimating and mitigating aging effects in routing network of FPGAs

Khaleghi, B ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/TVLSI.2018.2886326
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. In this paper, we present a comprehensive analysis of the impact of aging on the interconnection network of field-programmable gate arrays (FPGAs) and propose novel approaches to mitigate the aging effects on the routing network. We first show the insignificant impact of aging on data integrity of FPGAs, i.e., static noise margin and soft error rate of the configuration cells, as well as we show the negligible impact of the mentioned degradations on the FPGA performance. As such, we focus on the performance degradation of datapath transistors. In this regard, we propose a routing accompanied by a placement algorithm that prevents constant stress on transistors by evenly distributing the stress through the interconnection resources. By observing the impact of the signal probability on the aging of routing buffers, we enhance the synthesis flow as well as augment the proposed routing algorithm to converge the signal probabilities toward aging-friendly values. Experimental results over a set of industrial benchmarks and commerciallike FPGA architecture indicate the effectiveness of the proposed method with 64.3% reduction of stress duration in multiplexers and up to 45.2% improvement of the degradation of buffers. Altogether, the proposed method reduces the timing guardband by from 14.1% to 31.7%, depending on the FPGA routing architecture. © 1993-2012 IEEE
  6. Keywords:
  7. Aging ; Design automation ; SRAM cells ; Aging of materials ; Computer aided design ; Hot carriers ; Interconnection networks (circuit switching) ; Logic gates ; Network architecture ; Network routing ; Radiation hardening ; Reliability ; Static random access storage ; Comprehensive analysis ; Design automations ; Fpga routing architectures ; Interconnection resources ; Performance degradation ; Placement algorithm ; SRAM Cell ; Static noise margin ; Field programmable gate arrays (FPGA)
  8. Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 27, Issue 3 , 2019 , Pages 651-664 ; 10638210 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8610235