Loading...
- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 53115 (05)
- University: Sharif University of Technology
- Department: Electrical Engineering
- Advisor(s): Sharifbakhtiar, Mehrdad
- Abstract:
- In this thesis, we exploit N-path architecture in multi-standard transmitter in order to reduce the number of power amplifiers and matching networks. First, a new model of this transmitter is developed and simplified to improve its performance in operating frequency,power consumption and power efficiency . The model is then used for computer simulations of the proposed system for a variety of different modulations. Eight clock signals with consecutive phase difference of 2π/8 are generated by a divider and are applied to the power amplifier. The power amplifier is fullydigital. This removes the need for analog mixers and converts the transmitter to a fully digital transmitter. The proposed system was laid out in 0.18-μm CMOS with the die area of 0.81 . Post layout simulations of the transmitter with a power supply of 3.1 V verify output power of 15.6 dBm with efficiency of 11.2%, and error vector magnitude of -32.46 dBm for the 64 QAM-modulated signal. It operates from 200 MHz to 1500 MHz, while all of the harmonics are less than -41 dBc
- Keywords:
- Efficiency ; Harmonics ; N-Path Amplifier ; Multistandard Transmitter ; Digital Power Amplifier ; Impedance Matching
-
محتواي کتاب
- view