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Thermal Management in Fault-Tolerant Mixed-Criticality Multicore Systems

Gohari Nazari, Pourya | 2021

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 53735 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hessabi, Shahin
  7. Abstract:
  8. The increasing complexity of embedded systems has led to the integration of tasks with various degrees of criticality on a common hardware platform called a mixed-criticality system. These systems typically exploit the inherent redundancy of multicore systems to employ the fault-tolerant techniques to satisfy the required target reliability. On the other hand, the use of fault-tolerant techniques increases the time that cores are simultaneously active with maximum power, which can violate the thermal design power (TDP) and exceed the safe temperature of the chip. This activates the dynamic thermal manage- ment (DTM) technique. Some of the most well-known methods to reduce the chip surface temperature are: 1) increasing the chip fan rate, 2) reducing the chip frequency, and 3) cutting off the clock pulse of some parts of the chip. Continuous activation of the dynamic thermal management can significantly reduce the predefined level of performance which was achieved at design time during the scheduling of tasks in the system. This problem in mixed-criticality systems can increase execution time (which may lead to deadline violation), degrade reliability in tasks with a high degree of criticality, and thus cause disaster. In this research, we propose two distinct approaches to schedule graph-based mixed-criticality tasks on multi-core platforms with two different fault-tolerant techniques (NMR and task replication). Then we propose methods based on peak power consumption, to control the chip surface temperature below constraints, while in addition to satisfying the timing and reliability constraints, the maximum allowable surface temperature of the chip is managed
  9. Keywords:
  10. Thermal Management ; Multi-Core Platforms ; Mixed-Criticality Emdedded Systems ; Fault Tolerance ; Embedded System

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