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The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model

Goudarzi, M ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1016/j.micpro.2008.04.001
  3. Publisher: 2008
  4. Abstract:
  5. Design technology is expected to rise to electronic system-level (ESL). This necessitates new techniques and tools for synthesizing ESL designs and for verifying them before and after ESL synthesis. A promising verification strategy for future very complex designs is to initially verify the design at the highest level of abstraction, and then check the equivalence of the lower level automatically generated models against that initial golden model. We present one such approach to simulation-based functional verification implemented in our ESL design methodology called ODYSSEY. Our ESL synthesis tool generates a transaction-level model (TLM) at TLM level 2 (i.e., design with partial timing) that corresponds to the input ESL design (which is at TLM level 3; i.e., sole functionality without timing). Both the ESL design and its generated TLM model can be simulated on a host machine with corresponding input stimuli to establish their functional equivalence. The TLM is in SystemC, and hence executable, and also models both hardware and software components in C++ to achieve higher simulation speed. We introduce an implementation of a TLM level 2 model that is tailored to our ESL design methodology and apply our approach to a number of benchmarks to evaluate the TLM simulation performance. Experimental results show that the approach suits early validation of the ESL synthesis process since its simulation performance is more than 4 orders of magnitude higher than simulations at lower levels and it is generated early in the design cycle. Also the co-simulation overhead - compared to simulating the original ESL design in C++ - depends on the partitioning quality in terms of communication to computation ratio. © 2008 Elsevier B.V. All rights reserved
  6. Keywords:
  7. Benchmarking ; Channel capacity ; Chlorine compounds ; Complexation ; Computer programming languages ; Large scale systems ; Machine design ; Model checking ; Process engineering ; System theory ; Systems analysis ; Telecommunication networks ; Time measurement ; Unified Modeling Language ; Automatically generated ; Before and after ; Co-simulation ; Complex designs ; Design cycles ; Design technologies ; Electronic system-level ; Equivalence checking ; ESL design ; Functional equivalence ; Functional verifications ; Hardware and software components ; Hardware-software co-design ; Hardware-software co-simulation ; Level 2 ; Level model ; Level of abstraction ; New techniques ; ODYSSEY methodology ; Orders-of-magnitude ; Simulation performance ; Simulation speed ; Simulation-based ; Simulation-based verification ; Synthesis process ; Synthesis tools ; SystemC ; Transaction-level model ; Verification strategy ; Computer simulation
  8. Source: Microprocessors and Microsystems ; Volume 32, Issue 7 , 2008 , Pages 364-374 ; 01419331 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/abs/pii/S0141933108000392