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Design and synthesis of AKAM: A RISC asynchronous microprocessor
Mirza Aghatabar, M
Cataloging brief
Design and synthesis of AKAM: A RISC asynchronous microprocessor
Author :
Mirza Aghatabar, M
Publisher :
Pub. Year :
2007
Subjects :
Design Synthesis (chemical) Area overheads Asynchronous circuits Asynchronous designs ...
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2.4.1 Wireless Network Security Requirements
(19)
Access Control
(19)
Data Confidentiality
(19)
Data Authenticity
(20)
Data Integrity
(20)
Data Freshness
(20)
Availability
(21)
Secure Localization
(21)
2.4.2 Generic Wireless Network Attacks
(21)
2.4.3 External Attacks and Internal Attacks
(23)
2.4.4 Passive and Active Attacks
(23)
2.4.5 Denial of service attacks
(24)
3.1 hierarchy networking model
(25)
3.1.1 Node Hierarchy
(25)
3.1.2 Communication from BSN to DRN nodes
(26)
3.1.3 Communication from DRN to DDN nodes
(26)
3.1.4 Information discharge at DDN nodes
(27)
3.2 Node Addressing Scheme And Routing Protocols
(27)
3.2.1 Multi-Layer Addressing
(27)
3.2.2 Address Assignment
(28)
3.3 The routing algorithm at the DRN Nodes
(29)
3.3.3 Problem statement
(30)
Proposed Method
(32)
1.2 Design Principle
(32)
5.1 Omnet++
(45)
Conclusion and future work
(54)
References
(57)