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An assertion-based verification methodology for system-level design

Gharehbaghi, A. M ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1016/j.compeleceng.2007.02.002
  3. Publisher: 2007
  4. Abstract:
  5. In this paper, we integrate an assertion-based verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification. In this direction a system-level assertion language is defined. The system-level assertions can be used to monitor the current state of system or flow of transactions. These assertions are automatically converted to "monitor hardware" or "monitor software" during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertions, and hence, can be reused to verify the system after HW/SW synthesis and also at run-time after system manufacturing. This way, not only system-level assertions are reused in lower-levels of abstraction, but also run-time verification of system is provided. In this paper, we describe the system-level assertion language and explain the corresponding synthesis method in our object-oriented system-level synthesis methodology; however the concept can be applied to any system-level design methodology with modifications to assertion types and synthesis method. © 2007 Elsevier Ltd. All rights reserved
  6. Keywords:
  7. Automation ; Computer hardware ; Computer software ; Object oriented programming ; Problem solving ; Assertion-based verification ; System-level assertion ; System-level designs ; System-level verifications ; Systems analysis
  8. Source: Computers and Electrical Engineering ; Volume 33, Issue 4 , 2007 , Pages 269-284 ; 00457906 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/abs/pii/S0045790607000201