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Design and Efficient Implementation of Equalizer and Synchronizer Block in Recent Telecommunication Links Standards

Zeighami, Amir Mahdi | 2021

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 54568 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Shabany, Mahdi
  7. Abstract:
  8. Today, telecommunication links transmit information wirelessly at high rates; The transmission channel is not ideal and the transmitted signal undergoes changes in the channel and then reaches the receiver; Also, the processing blocks in the transmitter and receiver are not completely similar and ideal; These two factors make it difficult for the receiver to recover the transmitted information and actually receives a signal that bears little resemblance to the transmitted signal. The most important effect that the channel has on the transmitted signal is due to the multi-path of the channel between the transmitter and the receiver, which causes a signal to reach the receiver through the line-of-sight path and also several rays of the transmitted signal through other paths with more delay; This effect is called intersymbol interference. The second factor is that the transmitter and the receiver are not synchronized; This non-synchronization can be in time, frequency, phase and in frame where the standards in which information is sent in a form of a frame.Therefore, the two mentioned factors disrupt the information extraction process and in order to receive the correct information, it is necessary to eliminate the effects of these two factors as much as possible; A synchronizer block is used to eliminate the effects of transmitter and receiver not synchronizing, and an equalizer block is used to eliminate the effect of intersymbol interference.In this thesis, We proposed a structure for the equalizer and synchronizer block in recent telecommunication links standards and finally a structure for the physical layer of the digital receiver for DVB-S2 standard. Gardner algorithm is used for timing synchronization, improved multiplierless architecture for header detection for frame detection, two-stage carrier frequency offset compensation method for frequency synchronization which uses Fitz algorithm for coarse carrier recovery and Luise-Reggiani for fine carrier recovery and finally an adaptive filter for equalizer. Algorithms used in this receiver, may have more computational complexity and used more resources than conventional methods in order to support very-low signal-to-noise ratio. It should be noted that the presented structure is implemented on FPGA and the results are shown
  9. Keywords:
  10. Equalizer ; Digital Video Broadcasting (DVB) ; Field Programmable Gate Array (FPGA) ; Inter-Symbol Interference (ISI) ; Synchronizer ; Digital Telecommunication Receiver

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