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PF-DRAM: A precharge-free DRAM structure

Rohbani, N ; Sharif University of Technology | 2021

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  1. Type of Document: Article
  2. DOI: 10.1109/ISCA52012.2021.00019
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2021
  4. Abstract:
  5. Although DRAM capacity and bandwidth have increased sharply by the advances in technology and standards, its latency and energy per access have remained almost constant in recent generations. The main portion of DRAM power/energy is dissipated by Read, Write, and Refresh operations, all initiated by a Precharge phase. Precharge phase not only imposes a large amount of energy consumption, but also increases the delay of closing a row in a memory block to open another one. By reduction of row-hit rate in recent workloads, especially in multi-core systems, precharge rate increases which exacerbates DRAM power dissipation and access latency. This work proposes a novel DRAM structure, called Precharge-Free DRAM (PF-DRAM), that eliminates the Precharge phase of DRAM. PF-DRAM uses the charge on bitlines from the previous Activation phase, as the starting point for the next Activation. The difference between PF-DRAM and conventional DRAM structure is limited to precharge and equalizer circuitry and simple modifications in sense amplifier, which are all limited to subarray level. PF-DRAM is compatible with the mainstream JEDEC memory standards like DDRx and HBM, with minimum modifications in memory controller. Furthermore, almost all of the previously proposed power/energy reduction techniques in DRAM are still applicable to PF-DRAM for further improvement. Our experimental results on a 8GB memory system running SPEC CPU2017 and PARSEC2.1 workloads show an average of 35.3% memory power consumption reduction (up to 54.2%) achieved by the system using PF-DRAM with respect to the system using conventional DRAM. Moreover, the overall performance is improved by 8.6%, in average (up to 24.3%). According to our analysis, all such improvements are achieved for less than 9% area overhead. © 2021 IEEE
  6. Keywords:
  7. Chemical activation ; Energy utilization ; Memory architecture ; Memory controller ; Memory systems ; Multi-core systems ; Power consumption reduction ; Precharge phase ; Reduction techniques ; Sense amplifier ; Simple modifications ; Dynamic random access storage
  8. Source: 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, 14 June 2021 through 19 June 2021 ; Volume 2021-June , 2021 , Pages 126-138 ; 10636897 (ISSN); 9781665433334 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/9499892