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Total 73 records

    Analysis of the effects of clock imperfections in N-path filters

    , Article Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, 7 June 2015 through 10 June 2015 ; June , 2015 , Page(s): 1 - 4 ; 9781479988938 (ISBN) Nikoofard, A ; Kananian, S ; Khorami, A ; Fotowat Ahmady, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    In this paper, the effect of imperfections on the behavior of N-path filters is investigated. Exact mathematical derivations are presented which describe the effect of clock skew and finite fall/rise time on the impedance transformation behavior of N-path filters. In the ideal case, the N-path filter is supposed to provide a short-circuit to the ground for undesired frequency contents and an open-circuit for the desired signal so that it lies within the passband of the filter. It is shown that clock skew and finite clock fall/rise time result in a non-zero impedance for frequency contents other than the clock frequency and a smaller impedance for the desired voltage. In a real circuit with... 

    A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects

    , Article Integration ; Volume 69 , 2019 , Pages 321-334 ; 01679260 (ISSN) Sariri, H ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
    Elsevier B.V  2019
    Abstract
    This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is... 

    An efficient synchronization circuit in multi-rate SDH networks

    , Article Arabian Journal for Science and Engineering ; Volume 39, Issue 4 , April , 2014 , Pages 3101-3109 ; ISSN: 13198025 Zare, M ; Hessabi, S ; Goudarzi, M ; Sharif University of Technology
    Abstract
    Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are... 

    Seeking better times: Atomic clocks in the generalized Tonks-Girardeau regime

    , Article Journal of Physics: Conference Series ; Volume 99, Issue 1 , 2008 ; 17426588 (ISSN) Mousavi, S. V ; Del Campo, A ; Lizuain, I ; Pons, M ; Muga, J. G ; Sharif University of Technology
    Institute of Physics Publishing  2008
    Abstract
    First we discuss briefly the importance of time and time keeping, explaining the basic functioning of clocks in general and of atomic clocks based on Ramsey interferometry in particular. The usefulness of cold atoms is discussed, as well as their limits if Bose-Einstein condensates are used. We study as an alternative a different cold-atom regime: the Tonks-Girardeau (TG) gas of tightly confined and strongly interacting bosons. The TG gas is reviewed and then generalized for two-level atoms. Finally, we explore the combination of Ramsey interferometry and TG gases. © 2008 IOP Publishing Ltd  

    Analysis of imperfections in N-phase high-Q band-pass filters

    , Article IEEE International Symposium on Circuits and Systems, ISCAS 2015, 24 May 2015 through 27 May 2015 ; Volume 2015-July , May , 2015 , Pages 273-276 ; 02714310 (ISSN) ; 9781479983919 (ISBN) Nikoofard, A ; Kananian, S ; Behmanesh, B ; Atarodi, S. M ; Fotowat Ahmady, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    The effect of clock skew and duty-cycle on the performance of high-Q N-phase band-pass filters (BPFs) have been examined in this paper. Following a mathematical approach and using the analytical derivations carried out, the effects of such non-idealities as clock skew and duty-cycle error are determined in an N-path filter. It is analytically proved that image signals from all integer multiples of the clock signal, rather than just those at (1 ± kN) multiples of the clock signal, land atop the wanted RF spectrum. In a real world clock generator, with non-idealities in effect, filtering property and proper behavior of the filter is adversely affected. Finally, system level simulation along... 

    Behavioral modeling of clock feed-through and channel charge injection non-ideal effects in SIMULINK for switched-capacitor integrator

    , Article Simulation Modelling Practice and Theory ; Volume 18, Issue 5 , May , 2010 , Pages 483-499 ; 1569190X (ISSN) Torkzadeh, P ; Atarodi, M ; Sharif University of Technology
    2010
    Abstract
    Sigma-Delta modulator ADCs used in signal processing applications usually, are implemented by switched-capacitor (SC) circuits and CMOS transmission gates due to its simplicity for implementation. Channel charge injection (CCI) and clock feed-through (CFT) are two major non-ideal effects existing in TG switches and SC integrators reducing modulator total SNR, its linearity and its total gain. This paper presents a precise model for SC integrator including CCI and CFT non-ideal effects in MATLAB SIMULINK environment which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) Sigma-Delta modulators. Evaluation and validation of extracted models were... 

    A Low-power clock generator with a wide frequency tuning range and low temperature variation: analysis and design

    , Article Journal of Circuits, Systems and Computers ; Volume 29, Issue 1 , 2020 Fazel, Z ; Shokrekhodaei, M ; Atarodi, M ; Sharif University of Technology
    World Scientific Publishing Co. Pte Ltd  2020
    Abstract
    This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit... 

    Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance

    , Article IET Circuits, Devices and Systems ; Volume 2, Issue 5 , 2008 , Pages 409-421 ; 1751858X (ISSN) Sakian, P ; Saffari, M ; Atarodi, M ; Tajalli, A ; Sharif University of Technology
    2008
    Abstract
    A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 μm CMOS technology and operating in 10 Gbps... 

    Fully Digital Implementation and Optimization of Openhole Oil Well Surface Modem

    , M.Sc. Thesis Sharif University of Technology Shahbazi Dastgerdeh, Mehdi (Author) ; Movahedian, Hamid (Supervisor) ; Gholampour, Iman (Co-Supervisor)
    Abstract
    Once a well has been drilled before it is cased with the steels (open-hole well), some logging must be done to record information’s about layers, geologic formations, geophysical and petrophysical properties of well. All the information’s that gathered from sensors and tools transmitted to the surface by a down-hole modem. This information is corrupted during the transmission by the communication channel. The most notable influence of this channel is noise, attenuation and interference between successive data bits. On the other hand, the characteristic of channel changes with the length of the cable, temperature, connections and so on. So using a set of fixed filters is not effective. The... 

    Almost zero-jitter optical clock recovery using all-optical kerr shutter switching techniques

    , Article Journal of Lightwave Technology ; Volume 33, Issue 9 , February , 2015 , Pages 1737-1747 ; 07338724 (ISSN) Damani, R ; Salehi, J. A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    In this paper, a new all optical phase-locked loop (OPLL) is proposed and analyzed. The scheme relies on using two optical Kerr shutters to reveal the OPLL's error signal. The set of optical Kerr shutters and the subsequent low-speed photodetectors realize two nonlinear cross-correlations between the local clock pulse stream (called pump in Kerr shutter notations) and the time-shifted replicas of the incoming received data signal (called probe). The outputs of the cross-correlators are subtracted to form the error signal of the OPLL. We characterize the mathematical structure of the proposed OPLL and identify its two intrinsic sources of phase noise, namely, randomness of the received... 

    A low overhead fault detection and recovery method for the faults in clock generators

    , Article 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09, Chengdu, 28 April 2009 through 29 April 2009 ; 2009 ; 9781424425877 (ISBN) Karimpour Darav, N ; Amiri, M. A ; Ejlali, A ; Sharif University of Technology
    2009
    Abstract
    In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency oscillators because of their drawbacks so that it needs neither more effort to meet Electro-Magnetic Compatibility (EMC) and requirements nor extra hardware to implement DLLs. We have formally evaluated the meta-stability of our technique. This evaluation shows that our technique reliably... 

    Performance limits of optical clock recovery systems based on two-photon absorption detection scheme

    , Article IEEE Journal on Selected Topics in Quantum Electronics ; Volume 14, Issue 3 , 2008 , Pages 963-971 ; 1077260X (ISSN) Zarkoob, H ; Salehi, J. A ; Sharif University of Technology
    2008
    Abstract
    In this paper, we analyze and discuss the performance limits of optical clock recovery systems using a phase-locked loop (PLL) structure with nonlinear two-photon absorption (TPA) phase detection scheme. The motivation in analyzing the aforementioned optical PLL with TPA receiver structure is due to a recent successful experiment reported in [8]. We characterize the mathematical structure of PLLs with TPA, so as to evaluate the performance limits on optical clock recovery mechanism. More specifically, we identify two intrinsic sources of phase noise in the system namely, the ON-OFF nature of the incoming data pulses and the detector's shot noise that ultimately limit the performance of the... 

    P2R2: Parallel Pseudo-Round-Robin arbiter for high performance NoCs

    , Article Integration, the VLSI Journal ; November , 2014 ; ISSN: 1679260 Bashizade, R ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

    P2R2: Parallel Pseudo-Round-Robin arbiter for high performance NoCs

    , Article Integration, the VLSI Journal ; Volume 50 , 2014 , pp.173–182 ; ISSN: 0167-9260 Bashizade, R ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

    P2R2: Parallel pseudo-round-robin arbiter for high performance NoCs

    , Article Integration, the VLSI Journal ; Volume 50 , June , 2015 , Pages 173-182 ; 01679260 (ISSN) Bashizade, R ; Sarbazi Azad, H ; Sharif University of Technology
    Elsevier  2015
    Abstract
    Abstract Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

    Analysis and design of 4-path filter using gyrator based complex impedance

    , Article AEU - International Journal of Electronics and Communications ; Volume 70, Issue 11 , 2016 , Pages 1532-1542 ; 14348411 (ISSN) Karami, P ; Behmanesh, B ; Atarodi, S. M ; Sharif University of Technology
    Elsevier GmbH 
    Abstract
    A novel N-path filter using a complex impedance is designed to replace the frontend SAW filters in receivers with on-chip bandpass filters. It is demonstrated that the center frequency of the filter can be tuned solely by changing the value of some capacitances without the need to change the clock frequency. In addition, thanks to the use of smaller capacitors, the silicon area is reduced compared to similar designs. The high-Q bandpass filter is realized utilizing two gyrators and an arrangement of four baseband capacitors with NMOS switches, driven by 4-phase 25% duty cycle clock signals. This paper also analyzes the performance of the proposed filter against imperfections such as thermal... 

    A clock boosting scheme for low voltage circuits

    , Article 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, 31 August 2008 through 3 September 2008 ; 2008 , Pages 21-24 ; 9781424421824 (ISBN) Behradfar, A ; Zeinolabedinzadeh, S ; HajSadeghi, K ; Sharif University of Technology
    2008
    Abstract
    Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt. © 2008 IEEE  

    Assessment of message missing failures in FlexRay-based networks

    , Article 13th Pacific Rim International Symposium on Dependable Computing, PRDC 2007, Melbourne, VIC, 17 December 2007 through 19 December 2007 ; 2007 , Pages 191-194 ; 0769530540 (ISBN); 9780769530543 (ISBN) Lari, V ; Dehbashi, M ; Miremadi, S. G ; Farazmand, N ; Sharif University of Technology
    2007
    Abstract
    This paper assesses message missing failures in a FlexRay-based network. The assessment is based on about 35680 bit-flip fault injections inside different parts of the FlexRay communication controller; the parts are: controller host interface, protocol operation control, coding and decoding unit, media access control and clock synchronization process. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. This HDL model of the controller is exploited to setup a FlexRay-based network composed of four nodes. The results of fault injection show that about 35% of faults led to the message missing failures. The controller host interface and the clock... 

    Value-Aware low-power register file architecture

    , Article CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 44-49 ; 9781467314824 (ISBN) Ahmadian, S. N ; Fazeli, M ; Ghalaty, N. F ; Miremadi, S. G ; Sharif University of Technology
    2012
    Abstract
    In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, "Value-Aware Partitioned Register File (VAP-RF)", employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure  

    Fast SEU detection and correction in LUT configuration bits of sram-based FPGAs

    , Article 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Long Beach, CA, 26 March 2007 through 30 March 2007 ; 2007 ; 1424409101 (ISBN); 9781424409105 (ISBN) Zarandi, H.R ; Miremadi, S. G ; Argyrides, C ; Pradhan, D. K ; Sharif University of Technology
    2007
    Abstract
    FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter, detection and correction is performed in predefined error-correction intervals. In both of them error detections and corrections of k-input LUTs are performed with a latency of 2k clock cycle without any...