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Designing a 32-Bit Fault-Tolerant ALU Using EDAC
| 2011
1113
Viewed
- Type of Document: M.Sc. Thesis
- Language: English
- Document No: 41520 (55)
- University: Sharif University of Technology, International Campus, Kish Island
- Department: Science and Engineering
- Advisor(s): Vosughi Vahdat, Bijan; Mortazavi, Mohammad
- Abstract:
Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since the usages of the ARM (Advanced RISC Machine) processors are more applicable for the control system, we give the fault tolerance characteristic through the error control coding to this processor. As a result, the core for implementation of an ALU employing the BCH code on Spartan-3 FPGA has been provided. Our Fault tolerant ALU has high reliability. Also, it consumes low hardware overhead with acceptable fault coverage.
- Keywords:
- Fault Tolerance ; Arithmetic-Logic Unit (ALU) ; Encoder ; Decoding Algorithm ; Field Programmable Gate Array (FPGA) ; Bose, Chaudhuri and Hocquenghem (BCH)Code
Digital Object List-
محتواي پايان نامه - view
Bookmark- I would like to thank my supervisor, Dr. B. Vousughi Vahdat who was exceptionally considerate and offered immense insights and assistance. I would also like to specially thank my co-advisor, Dr. Mohammad Mortazavi for his support during my studies. I...
- I would like to thank ITRC (Iran Telecommunication Research Center) which has supported this work.
- Last; but not least, the author is heartily thankful to his beloved parents for their understanding and boundless love. They brought me up with their love and encouraged me to pursue an advanced degree. I would like to give my heartfelt appreciation t...
- Introduction
- Nowadays, by increasing the usage of digital systems and the improvement of modern technology, working on reliable communication transmission plays an important role. A single error may shutdown the whole system and give rise to incredible or erroneou...
- 1.4 Overview
- In Chapter 4, we have introduced the BCH coder including the encoder and decoder structure of BCH codes. Also, Implementation of a (63, 36) BCH codec is presented. Furthermore, the proposed method based on BCH code has been presented. First, implement...
- 2.3 Verilog Hardware description language and synthesis
- 2.4 Hardware solution
- 2.5 Finite fields or Galois field
- 2.5.1 Basic properties of Finite fields
- 2.5.2 The prime fields GF (P) and its extension GF (Pm)
- 2.5.3 The binary field GF(2) and its extension GF(2m)
- 2.5.4 Irreducible polynomial
- 2.5.5 The primitive polynomial and primitive elements
- 2.5.6 The minimal polynomial
- 2.6 Construction of Galois field GF(2m)
- 2.6.1 Structure of Galois field GF(26)
- 2.6.2 Computation using Galois field GF(26)
- In this chapter the proposed method based on the BCH code has been presented. First, the implementation of the Galois field arithmetic such as Adder and multiplying has been presented. Generator polynomial and codeword are explained and then binary BC...
- 4.1.1 Implementation of addition operation over two field elements
- 4.1.2 A circuit implementation for multiplying an arbitrary element by α
- 4.1.3 A circuit implementation for multiplication of two field elements
- 4.2 Introduction to BCH codes
- 4.2.1 Basic theory
- 4.2.2 Codeword
- 4.2.3 A generator polynomial of an (n, k) BCH code
- 4.2.4 Binary Primitive BCH codes
- 4.2.5 The structure of codeword for (63, 36) BCH code
- 4.4 An encoding for (n, k) BCH code
- 4.5 A decoding for (n, k) BCH code
- The decoding of BCH code is composed of three main steps that are described as follows:
- 4.5.1 The syndromes computation
- 4.5.2 Implementation of syndrome computation
- 4.5.3 Finding the error-locator polynomial
- For no error: σ(x) =1, s1=s3=0
- For one error: σ(x) =1+s1 x, s1≠ 0, s3=s13
- for no error and , then
- if only one error has took place and , then, .
- If there exist two errors and , then
- If and more than two errors have took place so, the position of error cannot be located and by this way cannot correct it [19].
- 4.5.5 Finding the error location numbers and error correction
- For no error: σ(x) =1, s1=s3=0
- For one error: σ(x) =1+s1 x, s1≠ 0, s3=s13
- for no error and , then
- .
- If only one error has taken place and , then, .
- If there exist two errors and , then
- If and more than two errors have took place so the position of error cannot be located and by this way cannot correct it [19].
- The generator polynomial of the (63,51) BCH code is shown in Fig. 4.6.
- 4.8 Hardware implementation of a (63, 36) BCH encoder and decoder for t=5
- 4.8.1 Parameter design of BCH code
- 4.8.2 Hardware implementation of a (63, 36) BCH encoder
- 4.8.3 Hardware implementation of a (63, 36) BCH decoder
- 5.1 Synthesis of 32-bit ALU system
- 5.1.1 32-bit Full-Adder RTL structure
- 5.3 Designing of 32-bit Fault Tolerant ALU
- 6.1 Suggestion for future search