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- Type of Document: Ph.D. Dissertation
- Language: Farsi
- Document No: 41930 (19)
- University: Sharif University of Technology
- Department: Computer Engineering
- Advisor(s): Miremadi, Ghasem
- Abstract:
In this thesis, we intend to propose low cost SED-tolerant techniques for different compo nents of embedded processors core including data path components such as register file and ALU as well as control path components such as control unit. Since the reliability es timation is the essential step in design of a fault-tolerant system, we propose fast and accu rate analytical soft error rate (SER) estimation techniques in Section 4. The proposed techniques have the ability to measure: 1) the SER of a design; 2) the SER of each indi vidual gate and FF, and 3) the SER of a specific path in the design. Using such infor mation, designers can selectively protect the vulnerable parts resulting in lower power and area overheads that are the most important factors in design of embedded systems. Unlike previous techniques, the proposed techniques firstly do not rely on fault injection or fault simulation; secondly they measure the SER for multi cycles of circuit operation; thirdly, the proposed techniques accurately compute all three masking factors, namely, logical, electrical, and timing masking; fourthly, the effects of error propagation in re-convergent fan-outs are considered in the proposed techniques. The SERs estimated by the proposed technique for some ISCAS89 circuit benchmarks are compared with that estimated by the Monte Carlo (MC) simulation based fault injection technique. The results show that the proposed techniques are orders of magnitude faster than the MC fault injection technique while having high level of accuracy. This level of fastness and accuracy makes the pro posed techniques viable solutions to measure the SER of industrial-scale circuits. Since latches and FFs are very critical parts of a sequential circuits, we focus on radiation hard ened latches and FFs in Section 5. In this section, we propose two radiation hardened FFs that have the ability to cancel out the effects of both Single Event Upset (SEU) and Single Event Transient (SET) faults. Extracting the most vulnerable FFs of a circuit using the proposed SER estimation techniques and employing the proposed hardened FFs instead of them, the SER of the circuit can be significantly reduced while having low area and power consumption overheads. To protect the vulnerable components of the processor data path components such as register file and ALU, we propose a selective protection approach based on architectural characteristics of the components. Using this approach, in section 6, we propose two low cost fault-tolerant techniques for register file and ALU of a typical embedded processor. Simulation results show that the proposed techniques significantly increase the reliability of the components while also offering the benefits of low power, area, and performance overheads.
- Keywords:
- Embedded System ; Embedded Processor ; Fault Tolerance ; Soft Error ; Soft Error Rate Estimation
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