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Implementation of the Digital Part of DVB-T Protocol with Reduced Power and Area

Mozafari, Hassan | 2011

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 42201 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hessabi, Shaahin; Sharifkhani, Mohammad
  7. Abstract:
  8. An implementation of Digital Section of a DVB-T receiver has been introduced in this research. Nowadays, low-power and area-efficient designs have proven their importance in IC design aspect, so many low-power and area efficient approaches have been considered in this implementation. This design has been segregated into independent blocks, and each of them has been designed respect to the design goals. After that, all these blocks linked together and a whole system design implemented in gate level, then downloaded into a FPGA (Field programmable Gate Array) to test the timing and functionality of implemented blocks. In this thesis, some innovations have been introduced. A new algorithm for Reed Solomon decoder has been designed, while it let us to design a specific decoder which meets the DVB-T constraints and consumes much less power and would be placed in a restricted area. In this implementation, the Viterbi block is designed so that needs fewer hardware resources, meanwhile the inner de interleaver in this design is structured to use as many as possible block memories in order to reduce the power and area costs. To be sure of correct functional operations and meeting the timing constraint of the standard, these blocks placed in their places and DVB-T data have been gotten from the air, then these blocks started to decode the signals, and a real-time TV stream has been shown on the screen by means of multimedia player devices. After be assured of accurate functional working of proposed design, the attributes of the proposed architecture is being mesuared. This work is done by aid of the Design Compiler. This tool let us to measure the power and the gate count of each designed block. So, we used this software and reported the area and the power consumption of the design.

  9. Keywords:
  10. Power Consumption ; Field Programmable Gate Array (FPGA) ; Digital Video Broadcasting (DVB) ; Reed-Solomon Code ; Viterbi Algorithm ; Low Area

 Digital Object List

  • پياده سازي بخش ديجيتال گيرنده ي قرارداد DVB-T، با رويكرد كاهش توان
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