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Transient Fault Detection in Embedded Processors using Built In Self-Test (BIST) Facilities

Ebrahimi, Mohammad | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43803 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghassem
  7. Abstract:
  8. Ever increasing applications of embedded systems have motivated designers to pay special atten-tion to the design requirements of such systems. Among embedded applications, safety-critical sys-tems have high reliability requirements as failures in such systems may endanger human life or re-sult in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. Reducing feature size, power supply voltage and also increasing operating frequency have increased the occurance rate of transient faults in such processors. Built in Self-Test facilities available in many of embedded systems forms about 70% of total cost in such systems, but these facilities are idle during system normal operation. This thesis proposes a fault-tolerant method, called SScMC, that uses built in self-test facilities during the system normal operation. The proposed method is based on Master/Checker architecture in which both modules are employing shadow scan chain as this is a common test facility. The ability of cor-recting transient faults as well as latent faults in the SScMC method distinguishes it from conven-tional Master/Checker architectures. Usually conventional Master/Checker architectures use roll-back recovery mechanism to recover the system. However, the SScMC method uses roll forward mechanism which decreases the recovery time. This feature is an advantage in real time applica-tions where deadlines should be met. By comparing the scan chain of both Master and Checker modules, the controller is able to locate and correct the faulty module. The correction is performed by copying the current contents of FFs in the fault-free module to the erroneous one. The experi-mental results reveal that the proposed technique imposes about 40% less area overhead as com-pared with conventional Master/Checker techniques. The performance loss is about 5%
  9. Keywords:
  10. Fault Tolerance ; Transient Faults ; Scan Chain ; Embedded Processor ; Built-in Self-Test

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