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Prolonging Lifetime of a STT-RAM Last-Level Cache in a Multi-Core Chip Multi-Processor

Jokar, Mohamad Reza | 2014

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 46021 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. Emerging non-volatile memory technologies such as Spin- Transfer Torque RAM (STT-RAM) or Resistive RAM (ReRAM) can increase the capacity of the last-level cache (LLC) in a latency and power-efficient manner. These technologies endure between 109 to 1012 writes per cell, making a non-volatile cache (NV-cache) with a lifetime of dozens of years under ideal conditions. However, non-uniformity in writes to different cache lines can considerably reduce the NV-cache lifetime to few months. Writes to cache lines can be made uniformly with wear-leveling. A suitable wear-leveling for NV-cache should not incur high storage and performance overheads. We propose a novel, simple, and effective wear-leveling technique with negligible overall performance overhead of less than 0.4% for memoryintensive work-loads. Our proposal consists of two mechanisms: 1) a wear-leveling mechanism within each cache set that slightly increases main memory write-back traffic and LLC miss rates, and 2) a novel technique to reduce cache inter-set variations which causes minimum interference with normal cache operation. By using these mechanisms, we show that the lifetime of the baseline NV-cache is boosted up to 7x (3.5x, on average) for a two-level cache configuration
  9. Keywords:
  10. Nonvolatile Memory ; Wear Leveling ; On-Chip Multiprocessor ; Spin Transfer Torque-Magnetic (STT-MRAM) ; Write Endurance

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