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Low cost concurrent error detection for on-chip memory based embedded processors

Khosravi, F ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/EUC.2011.47
  3. Abstract:
  4. This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions and generate signatures for the running program, and 2) an external watchdog processor to compare runtime signatures and branch addresses with the information extracted offline. The proposed method is implemented on an embedded processor core and is evaluated by a simulation based statistical fault injection approach where faults are injected into cache and main memory. Experimental results show that the proposed method detects more than 96.7% of all errors with only 2.6% overhead in area and less than 1% increase in power consumption. Furthermore, this technique imposes almost no performance degradation
  5. Keywords:
  6. Concurrent error detection methods ; External watchdog processor ; Branch instructions ; Concurrent error detection ; Control flow checking ; Embedded processors ; Fault injection ; Hardware components ; Hardware modules ; Low costs ; Main memory ; Offline ; On chip memory ; On chips ; Performance degradation ; Runtimes ; Simulation-based ; Watchdog processors ; Cache memory ; Concurrency control ; Convolutional codes ; Human computer interaction ; Program processors ; Ubiquitous computing ; Error detection
  7. Source: Proceedings - 2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011, 24 October 2011 through 26 October 2011 ; October , 2011 , Pages 114-119 ; 9780769545523 (ISBN)
  8. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6104515