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A2CM2: Aging-aware cache memory management technique

Nazari, R ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1109/RTEST.2015.7369845
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2015
  4. Abstract:
  5. Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most prone modules to NBTI. Variations in duty cycle and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and distributes uniformly stress condition for each line. The simulation results show that the proposed technique reduces the NBTI effect in I-cache significantly as compared to normal operation. Moreover, the energy consumption and the performance overheads of the proposed technique are negligible
  6. Keywords:
  7. Cache memory ; CMOS integrated circuits ; Embedded systems ; Energy utilization ; Industrial management ; Negative temperature coefficient ; Static random access storage ; Thermodynamic stability ; Aging effects ; Cache management techniques ; Duty cycle balancing ; Instruction caches ; Memory management techniques ; Negative bias temperature instability ; Normal operations ; Performance and reliabilities ; Real time systems
  8. Source: CSI Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2015, 7 October 2015 through 8 October 2015 ; October , 2015 , Page(s): 1 - 8 ; 9781467380478 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7369845