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Accelerated on-chip communication test methodology using a novel high-level fault model

Karimi, E ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1109/MCSoC.2015.46
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2015
  4. Abstract:
  5. A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement
  6. Keywords:
  7. SoC ; State graph ; Buses ; Graphic methods ; Programmable logic controllers ; System-on-chip ; AMBA bus ; Complementary graph ; Extensive simulations ; Fault model ; Graph-based techniques ; High-level fault models ; On chip communication ; State graphs ; Testing
  8. Source: Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015, 23 September 2015 through 25 September 2015 ; 2015 , Pages 283-288 ; 9781479986699 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7328216