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VLSI implementation of a hardware-optimized lattice reduction algorithm for WiMAX/LTE MIMO detection

Youssef, A ; Sharif University of Technology | 2010

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  1. Type of Document: Article
  2. DOI: 10.1109/ISCAS.2010.5537810
  3. Publisher: 2010
  4. Abstract:
  5. This paper presents the first ASIC implementation of an LR algorithm which achieves ML diversity. The VLSI implementation is based on a novel hardware-optimized LLL algorithm that has 70% lower complexity than the traditional complex LLL algorithm. This reduction is achieved by replacing all the computationally intensive CLLL operations (multiplication, division and square root) with low-complexity additions and comparisons. The VLSI implementation uses a pipelined architecture that produces an LR-reduced matrix every 40 cycles, which is a 60% reduction compared to current implementations. The proposed design was synthesized in both 130μm and 65nm CMOS resulting in clock speeds of 332MHz and 833MHz, respectively. The 65nm result is a 4X improvement over the fastest LR implementation to date. The proposed LR implementation is able to sustain a throughput of 2Gbps, thus achieving the high data rates required by future standards such as IEEE 802.16m (WiMAX) and LTE-Advanced
  6. Keywords:
  7. Clock speed ; High data rate ; Ieee 802.16m ; Lattice reduction ; LLL algorithm ; Low-complexity ; Lower complexity ; LTE-Advanced ; MIMO detection ; Novel hardware ; Pipelined architecture ; Reduced matrix ; Square roots ; VLSI implementation ; Algorithms ; Fabrics ; Optimization ; Wimax ; VLSI circuits
  8. Source: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 30 May 2010 through 2 June 2010, Paris ; 2010 , Pages 3541-3544 ; 9781424453085 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/5537810/?reload=true