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VLSI implementation of a WiMAX/LTE compliant low-complexity high-throughput soft-output K-best MIMO detector

Patel, D ; Sharif University of Technology | 2010

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  1. Type of Document: Article
  2. DOI: 10.1109/ISCAS.2010.5537524
  3. Publisher: 2010
  4. Abstract:
  5. This paper presents a VLSI architecture of a novel softoutput K-Best MIMO detector. The proposed detector attains low computational complexity using three improvement ideas: relevant discarded paths selection, last stage on-demand expansion, and relaxed LLR computation. A deeply pipelined architecture for a soft-output MIMO detector is implemented for a 4x4 64-QAM MIMO system realizing a peak throughput of 655Mbps, while consuming 174K gates and 195mW in 0.13um CMOS. Synthesis results in 65nm CMOS show the potential to support a sustained throughput up to 2Gbps achieving the data rates envisioned by emerging IEEE 802.16m and LTE-Advanced wireless standards
  6. Keywords:
  7. Data rates ; High-throughput ; Ieee 802.16m ; Last stage ; Low-complexity ; LTE-Advanced ; MIMO detectors ; Pipelined architecture ; Soft output ; VLSI architectures ; VLSI implementation ; Wireless standards ; Computational complexity ; Detectors ; Fabrics ; MIMO systems ; Throughput ; VLSI circuits
  8. Source: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 30 May 2010 through 2 June 2010, Paris ; 2010 , Pages 593-596 ; 9781424453085 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/5537524