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Neda: supporting direct inter-core neighbor data exchange in GPUs

Nematollahi, N ; Sharif University of Technology | 2018

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  1. Type of Document: Article
  2. DOI: 10.1109/LCA.2018.2873679
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2018
  4. Abstract:
  5. Image processing applications employ various filters for several purposes, such as enhancing the images and extracting the features. Recent studies show that filters in image processing applications take a substantial amount of the execution time, and it is crucial to boost their performance to improve the overall performance of the image processing applications. Image processing filters require a significant amount of data sharing among threads which are in charge of filtering neighbor pixels. Graphics Processing Units (GPUs) attempt to satisfy the demand of data sharing by providing the scratch-pad memory, shuffle instructions, and on-chip caches. However, we observe that these mechanisms are insufficient to provide a fast and energy-efficient neighbor data sharing for the image processing filters. In this paper, we propose a new hardware/software co-design mechanism for GPUs, to effectively provide a fast and energy-efficient register-level neighbor data sharing for the image filters. We propose a neighbor data exchange mechanism, called Neda, that adds a register to each streaming processor (SP) which can be accessed by its neighboring SPs. Our experimental results show that Neda improves the performance and energy consumption by 12.4 and 13.5 percent, on average, respectively, compared to the NVIDIA SDK implementation of image processing filters. Moreover, Neda's performance is within 9.3 percent of the ideal GPU with zero latency neighbor data exchange capability. © 2002-2011 IEEE
  6. Keywords:
  7. GPUs ; Inter-core communication ; Neighbor data exchange ; Spatial image processing filters ; Computer graphics ; Computer hardware ; Electronic data interchange ; Energy efficiency ; Energy utilization ; Graphics processing unit ; Hardware-software codesign ; Image enhancement ; Image processing ; Program processors ; Instruction set ; Inter-core communications ; Microsoft windows ; Registers ; Spatial images ; Two-dimensional displays ; Computer architecture
  8. Source: IEEE Computer Architecture Letters ; Volume 17, Issue 2 , 2018 , Pages 225-229 ; 15566056 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8481514