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AM3D: An accurate crosstalk probability modeling to predict channel delay in 3D ICs

Shirmohammadi, Z ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1016/j.microrel.2019.06.071
  3. Publisher: Elsevier Ltd , 2019
  4. Abstract:
  5. Migration from Two Dimensional Integrated Circuits (2D ICs) to Three Dimensional Integrated Circuits (3D ICs) reduces the delay due to the shorter wire length between sender and receiver. However, Through-Silicon-Vias (TSVs) that connect layers in the structure of 3D ICs can seriously increase the delay due to capacitance coupling between TSVs and lead to crosstalk fault. The severity of crosstalk faults depends on transitions appearing on TSVs that is called transition patterns. To propose an efficient crosstalk tackling mechanisms in 3D ICs, an accurate probability analytical model is required to predict the delay caused by TSVs (3D ICs) in the attendance of these transition patterns. In this regard, this paper proposes an accurate crosstalk probability model for 3D ICs called AM3D that estimates the latency of communication channels of 3D ICs in the attendance of crosstalk faults. The model is applicable for both non-protected TSVs and TSVs which are protected by crosstalk mitigation mechanisms. In order to accredit our proposed model, various SPICE simulations are conducted and obtained outcomes in different benchmarks are compared with extracted results from AM3D. Comparisons present an average of 1.81% discrepancies between the time delay obtained from SPICE simulations and time delay calculated by our proposed model. © 2019 Elsevier Ltd
  6. Keywords:
  7. 3D ICs ; Crosstalk fault modeling ; Through-Silicon-Vias (TSV) ; Time delay ; 3D modeling ; Crosstalk ; Delay circuits ; Electronics packaging ; Integrated circuit interconnects ; Probability ; SPICE ; Time delay ; Timing circuits ; 3-D ICs ; Capacitance coupling ; Crosstalk fault ; Crosstalk mitigation ; Probability modeling ; Sender and receivers ; Through silicon vias ; Transition patterns ; Three dimensional integrated circuits
  8. Source: Microelectronics Reliability ; Volume 102 , 2019 ; 00262714 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/abs/pii/S0026271419303191