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Lazy instruction scheduling: Keeping performance, reducing power

Mahjur, A ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1145/1393921.1394020
  3. Publisher: 2008
  4. Abstract:
  5. An important approach to reduce power dissipation is reducing the number of instructions executed by the processor. To achieve this goal, this paper introduces a novel instruction scheduling algorithm that executes an instruction only when its result is required by another instruction. In this manner, it not only does not execute useless instructions, but also reduces the number of instructions executed after a mispredicted branch. The cost of the extra hardware is 161 bytes for 128 instruction window size. Measurements done using SPEC CPU 2000 benchmarks show that the average number of executed instructions is reduced by 13.5% while the average IPC is not affected. Copyright 2008 ACM
  6. Keywords:
  7. Low power electronics ; Power electronics ; Average numbers ; Dead instruction elimination ; Dynamic instruction scheduling ; Executed instructions ; Instruction scheduling ; Instruction scheduling algorithms ; Instruction windows ; Microarchitecture ; Power dissipations ; Reducing power ; Scheduling
  8. Source: ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design, Bangalore, 11 August 2008 through 13 August 2008 ; 2008 , Pages 375-380 ; 15334678 (ISSN); 9781605581095 (ISBN)
  9. URL: https://dl.acm.org/doi/10.1145/1393921.1394020