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Arithmetic circuits verification without looking for internal equivalences

Sarbishei, O ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1109/MEMCOD.2008.4547681
  3. Publisher: 2008
  4. Abstract:
  5. In this paper, we propose a novel approach to extract a network of half adders from the gate-level net-list of an addition circuit while no internal equivalences exist. The technique begins with a gatelevel net-list and tries to map it into word-level adders based on an efficient bit-level adder representation. It will be shown that the proposed technique is suitable for several gate-level architectures of multipliers, as it extracts adder components in a step-wise method. This approach can also be generalized to other arithmetic circuits. In order to evaluate the effectiveness of our approach, we run it on several arithmetic circuits and compare experimental results with those of contemporary techniques. © 2008 IEEE
  6. Keywords:
  7. Cobalt ; Cobalt compounds ; Computer networks ; Digital arithmetic ; Integrating circuits ; Logic circuits ; Networks (circuits) ; Arithmetic circuits ; International conferences ; Formal methods
  8. Source: 2008 6th ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'08, Anaheim, CA, 5 June 2008 through 7 June 2008 ; 2008 , Pages 7-16 ; 9781424424177 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4547681