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The shuffle-exchange mesh topology for 3D NoCs

Sharifi, A ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1109/I-SPAN.2008.23
  3. Publisher: 2008
  4. Abstract:
  5. Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh and torus topologies, other structures can also be considered especially in 3D VLSI design. The shuffle-exchange topology is one of the popular interconnection architectures for multiprocessors due to its scalability and self-routing capability. By vertically stacking two or more silicon wafers, connected with a high-density and high-speed interconnect, it is now possible to combine multiple active device layers within a single IC. In this paper we propose an efficient three dimensional layout for a novel 2D mesh structure based on the shuffle-exchange topology. Simulation results show that by using the third dimension, performance and latency can be improved compared to the 2D VLSI implementation. © 2008 IEEE
  6. Keywords:
  7. Decoding ; Nonmetals ; Parallel algorithms ; Parallel processing systems ; Silicon ; Silicon wafers ; Three dimensional ; 3-D VLSI ; Active device layers ; High speeds ; High-density ; IC designs ; Interconnection architectures ; International symposium ; Mesh structures ; Mesh topologies ; Networks on chips ; Parallel architectures ; Self-routing ; Simulation results ; Three-dimensional layout ; VLSI implementation ; Topology
  8. Source: Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN, 7 May 2008 through 9 May 2008, Sydney, NSW ; 2008 , Pages 275-280 ; 9780769531250 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4520227