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Fast SEU detection and correction in LUT configuration bits of sram-based FPGAs

Zarandi, H.R ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1109/IPDPS.2007.370378
  3. Publisher: 2007
  4. Abstract:
  5. FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter, detection and correction is performed in predefined error-correction intervals. In both of them error detections and corrections of k-input LUTs are performed with a latency of 2k clock cycle without any required reconfiguration and significant area overhead. The power and area analysis of the proposed techniques show that these methods are more efficient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs. © 2007 IEEE
  6. Keywords:
  7. Codes (symbols) ; Error correction ; Orbits ; Remote sensing ; Static random access storage ; Clock cycles ; Correction cycles ; Field programmable gate arrays (FPGA)
  8. Source: 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Long Beach, CA, 26 March 2007 through 30 March 2007 ; 2007 ; 1424409101 (ISBN); 9781424409105 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4228106