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Power consumption and performance analysis of 3D NoCs

Sharifi, A ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1007/978-3-540-74309-5_21
  3. Publisher: Springer Verlag , 2007
  4. Abstract:
  5. Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. Much research has been done in this field of study recently, e.g. in routing algorithms, switching methods, VLSI Layout, and effects of resource allocation on system performance. On the other hand, three-dimensional integrated circuits allow a time-warp for Moore's Law. By vertically stacking two or more silicon wafers, connected with a high-density, high-speed interconnect, it is now possible to combine multiple active device layers within a single IC. In this paper, we examine performance and power consumption in a three dimensional network-on-chip structure under different types of traffic loads, routing algorithms, and switching methods. To the best of our knowledge, this is the first work dealing with 3D NoCs implemented in a 3D VLSI model. © Springer-Verlag Berlin Heidelberg 2007
  6. Keywords:
  7. Electric power utilization ; Resource allocation ; Routing algorithms ; Silicon wafers ; High-speed interconnect ; Moore's Law ; Networks-on-chip (NoC) ; Integrated circuits
  8. Source: 12th Asia-Pacific Computer Systems Architecture Conference, ACSAC 2007, Seoul, 23 August 2007 through 25 August 2007 ; Volume 4697 LNCS , 2007 , Pages 209-219 ; 03029743 (ISSN); 9783540743088 (ISBN)
  9. URL: https://link.springer.com/chapter/10.1007%2F978-3-540-74309-5_21