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A 7 bit, 3 GHz bandwidth random-time-interleaved-hybrid DAC using a novel self-healing structure for DCE in 65 nm CMOS technology

Sariri, H ; Sharif University of Technology | 2021

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  1. Type of Document: Article
  2. DOI: 10.1016/j.aeue.2021.153617
  3. Publisher: Elsevier GmbH , 2021
  4. Abstract:
  5. The application of time-interleaved structure leads to new amplitude and time errors while reducing many static and dynamic errors. In this case, both amplitude and time error are decreased by circuit structures integrated into a 7-bit DAC. In the present study, a new structure was proposed based on the randomization of two-interleaved paths in order to reduce the amplitude error, which can be extended to the N-channels-interleaved. In order to reduce the cycle-duty-error, a self-correction structure based on calculating the amplitude of the error before and measuring the time of this error along with the passage of the main signal through the output multiplexer is provided. The advantage of this method compared to the previous ones is that it does not require any calibration. This approach improves SFDR up to 37.8 dB at the 3 GHz signal bandwidth. The Post-Layout-Simulation for a 7-bit Hybrid-Time-Interleaved DAC confirmed the above. © 2021 Elsevier GmbH
  6. Keywords:
  7. Bandwidth ; CMOS integrated circuits ; Delta sigma modulation ; Modulators ; 65 nm CMOS technologies ; Amplitude errors ; Circuit structures ; Delta sigma modulator ; Duty cycle error ; Hybrid DAC ; Self-healing structure ; Static and dynamic errors ; Time-interleaved ; Time-interleaving ; Errors
  8. Source: AEU - International Journal of Electronics and Communications ; Volume 134 , 2021 ; 14348411 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/abs/pii/S1434841121000145