Sharif Digital Repository

A high-precision delay chain circuit integrated in a 0.18- mu ext{m} CMOS technology working in the frequency bandwidth of 8-18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay... 

A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 μ m CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from... 

Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise  

A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125-and 3.9-ps delay resolution, designed and fabricated in a 0.18-μ m CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay blocks which the five main bits are based on novel delay structures. The proposed delay structures are similar to second-, fourth-, and sixth-order all-pass networks and are robust to mismatch effects of resistive parasitics of transistor switches. Measurement results of the fabricated delay chain show 15.2-23.3-dB insertion loss and less than 3.3-ps rms delay error over the intended frequency band from 8-18... 

A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125-and 3.9-ps delay resolution, designed and fabricated in a 0.18-μ m CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay blocks which the five main bits are based on novel delay structures. The proposed delay structures are similar to second-, fourth-, and sixth-order all-pass networks and are robust to mismatch effects of resistive parasitics of transistor switches. Measurement results of the fabricated delay chain show 15.2-23.3-dB insertion loss and less than 3.3-ps rms delay error over the intended frequency band from 8-18...