Sharif Digital Repository

In this paper, we study transmission of a memoryless Laplacian source over three types of channels: additive white Laplacian noise (AWLN), additive white Gaussian noise (AWGN), and slow flat-fading Rayleigh channels under both bandwidth compression and bandwidth expansion. For this purpose, we analyze two well-known hybrid digital-analog (HDA) joint source-channel coding schemes for bandwidth compression and one for bandwidth expansion. Then we obtain achievable (absolute-error) distortion regions of the HDA schemes for the matched signal-to-noise ratio (SNR) case as well as the mismatched SNR scenario. Using numerical examples, it is shown that these schemes can achieve a distortion very... 

We study transmission of a memoryless Laplacian source over an average-power limited additive white Laplacian noise (AWLN) channel under bandwidth compression in two cases: 1) matched signal-to-noise ratio (SNR), 2) mismatched SNR. A hybrid digital-analog (HDA) joint source-channel coding (JSCC) scheme is proposed and show that this scheme can achieve a distortion very close to the lower bound on mean-absolute error (MAE) distortion under matched SNR conditions  

A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous... 

We consider transmission of a Gaussian source over a Gaussian channel under bandwidth compression in the presence of an interference known only to the transmitter. We study hybrid digital-analog (HDA) joint source-channel coding schemes and propose two novel layered coding schemes that achieve the optimal mean-squared error (MSE) distortion. This can be viewed as the extension of results by Wilson ["Joint Source Channel Coding With Side Information Using Hybrid Digital Analog Codes," IEEE Trans. Inf. Theory, vol. 56, no. 10, pp. 4922-2940, Oct. 2010], originally proposed for sending a Gaussian source over a Gaussian channel in two cases: 1) Matched bandwidth with known interference only at... 

In this paper, we consider transmission of a Gaussian source over a Gaussian channel under bandwidth compression in the presence of interference known only to the transmitter. We study hybrid digital-analog (HDA) joint source-channel coding schemes and propose two novel coding schemes that achieve the optimal mean-squared error (MSE) distortion. This can be viewed as the extension of results by Wilson et al. [1], originally proposed for sending a Gaussian source over a Gaussian channel in two cases: 1) Matched bandwidth with known interference only at the transmitter, 2) bandwidth compression where there is no interference in the channel. The proposed HDA codes can cancel the interference of... 

We consider the problem of sending a bivariate Gaussian source S=(S 1,S 2) across a power-limited two-user Gaussian broadcast channel. User i (i=1,2) observes the transmitted signal corrupted by Gaussian noise with power σ i 2 and desires to estimate S i. We study hybrid digital-analog (HDA) joint source-channel coding schemes and analyze the region of (squared-error) distortion pairs that are simultaneously achievable. Two cases are considered: 1) broadcasting with bandwidth compression, and 2) broadcasting with bandwidth expansion. We modify and adapt HDA schemes of Wilson et al. and Prabhakaran et al. , originally proposed for broadcasting a single common Gaussian source, in order to... 

An efficient layout technique is proposed to eliminate the effect of the bottom-plate capacitors in a C-2C Digital to Analog Converter (DAC). Using this technique, the bottom-plate capacitors of 2C capacitors in the C-2C structure are placed in parallel with 1C capacitors. Then, the effect of the bottom plate capacitors is nulled by modifying the size of the main 1C capacitors. Hence, avoiding the complexity of calibration, this technique can preclude the effect of the bottom-plate to ground capacitance. Statistical simulations prove that the proposed technique is robust to non-ideal effects such as mismatch or parasitic capacitors. A 10-bit C-2C DAC is modeled in COMSOL Multiphysics using... 

A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply  

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise  

A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©... 

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes.... 

A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC. © 2017 IEEE