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    Design and Implementation of Fault-Tolerance Mechanisms for Scratch-Pad Memories (SPM) in Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Farbeh, Hamed (Author) ; Miremadi, Ghassem (Supervisor)
    Abstract
    Energy consumption, area, reliability and predictability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories has an increasing role to satisfy these limitations. SPM as an on-chip SRAM memory is highly vulnerable to soft errors and as it contains the most frequently used blocks of the program, errors in SPM can easily propagate in system leading to erroneous results. This thesis proposes two approaches to protect the SPM against soft errors. The first approach, MM-SPM, proposed to protect the instruction SPM and the second approach, CR-SPM, proposed to protect dynamically mapped data and instructions to the SPM. The main idea behind the... 

    Design and Evaluation of a Master/Checker Method for an Embedded Processor

    , M.Sc. Thesis Sharif University of Technology Ebrahimi, Mojtaba (Author) ; Miremadi, Ghasem (Supervisor)
    Abstract
    Ever increasing applications of embedded systems have motivated the designers to pay special attention to the design requirements of such systems. Among embedded applications, safety-critical systems have high reliability requirements as failures in such systems may endanger human life or result in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. This is because; a failure in the processor most probably leads to a system failure. One effective way to protect embedded processors against environmental faults is to use system level fault-tolerant techniques such as Master/Checker (M/C) or Triple Modular... 

    , Ph.D. Dissertation Sharif University of Technology Fazeli, Mahdi (Author) ; Miremadi, Ghasem (Supervisor)
    Abstract

    In this thesis, we intend to propose low cost SED-tolerant techniques for different compo­ nents of embedded processors core including data path components such as register file and ALU as well as control path components such as control unit. Since the reliability es­ timation is the essential step in design of a fault-tolerant system, we propose fast and accu­ rate analytical soft error rate (SER) estimation techniques in Section 4. The proposed techniques have the ability to measure: 1) the SER of a design; 2) the SER of each indi­ vidual gate and FF, and 3) the SER of a specific path in the design. Using such infor­ mation, designers can selectively protect the vulnerable parts... 

    , M.Sc. Thesis Sharif University of Technology Jahanghir, Elahe (Author) ; Jahed, Mehran (Supervisor) ; Miremadi, Ghasem (Supervisor)
    Abstract
    Considering ever expanding applications of embedded systems in all aspects of human life, reliability and fault tolerance of these systems have become vital. To increase the reliability in a microprocessor as the most critical component of an embedded system, one may notice the essential role that is offered by its register bank. In fact the register bank is the most critical subcomponent of an embedded system, greatly affecting the reliability of the overall system. The operation of the embedded system is further critically affected through optimal and efficient usage of power as most systems relay on battery. In this project, to evaluate the availability of register banks various... 

    Physical Fault Injection Methods for Evaluation of Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Shabahang, Soha (Author) ; Hemmatyar, Ali Mohammad Afshin (Supervisor)
    Abstract
    In order to ensure the Immunity of integrated circuits against electromagnetic interference, integrated circuits should go under the sensitivity measurement test. This test consists of radiation or directly injecting electromagnetic interference. Injected disturbances are applied, either to the whole device or to one part of the device under test. Standard 62132 describes the specification of the methods for determining the sensitivity in frequencies between 150 kHz to 1 GHz. To provide a method which is capable of implementing and is controllable, it is necessary to study the standard models, and examine and discuss the strengths and weaknesses of each from the point of performance and... 

    Configurable Description of Memory Organization for Low-Energy and Fault-Tolerant Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Taheri, Somayye (Author) ; Ejlali, Alireza (Supervisor)
    Abstract
    Memory organization plays an important role in embedded systems. Among the various component, memories as principle of consumption large amount of energy, are more important in power consumption, real time feature and fault tolerant of system.so that depend on system application, various configuration of memory organization are used…………. Memory organization issues include memory size, memory management methods, hardware management unit, cache, SPM and theirs subject and so on. This thesis discussed important topics related to energy consumption, real time and fault tolerant feature in memory organization and purposed a Configurable Description of Memory Organization for Low-Energy and... 

    Transient Fault Detection in Embedded Processors using Built In Self-Test (BIST) Facilities

    , M.Sc. Thesis Sharif University of Technology Ebrahimi, Mohammad (Author) ; Miremadi, Ghassem (Supervisor)
    Abstract
    Ever increasing applications of embedded systems have motivated designers to pay special atten-tion to the design requirements of such systems. Among embedded applications, safety-critical sys-tems have high reliability requirements as failures in such systems may endanger human life or re-sult in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. Reducing feature size, power supply voltage and also increasing operating frequency have increased the occurance rate of transient faults in such processors. Built in Self-Test facilities available in many of embedded systems forms about 70% of total cost in... 

    Workload-aware Fault-injection for Speeding-up Evaluation of the Dependable Systems

    , M.Sc. Thesis Sharif University of Technology Javani Jananlu, Saeid (Author) ; Miremadi, Ghassem (Supervisor)
    Abstract
    Dependability assessment is an important preliminary in the design of dependable systems. Simulation Based Fault Injection (SBFI) is a common way to evaluate system dependability. To achieve high accuracy in SBFI, a large amount number of fault injection is required, which is very time consuming. Many of ideas are implied to solve this disadvantage of SBFI. In this work, we propose a method that uses information of workload execution on the processor to reduce faults to be injected during the SBFI campaign. We concentrate on Single Event Upsets because of its majority and repeating interval. Our proposed method first gathers information about various regions of the processor by probing... 

    Including Facilities in an Embedded Processor for External Watchdog Processors

    , M.Sc. Thesis Sharif University of Technology Khosravi, Faramarz (Author) ; Miremadi, Ghassem (Supervisor)
    Abstract
    The wide range of embedded processors and their reliance on nano-scale technologyhave brought them serious concerns on reliability, power consumption, timeliness and cost. Therefore, theseconcernsmust be addressed at the design process withemploying minimum facilities.This thesis proposes a low-cost concurrent error detection method based on control flow checking suitable for embedded processors. Most of the previous control flow checking methods either do not consider the embedded processors concerns, or they are not applicable to processors with on-chip cache memories.The key idea behind the proposed control flow checking method is to embed specific hardware components in the IP core of an... 

    , M.Sc. Thesis Sharif University of Technology Mansouri, Ahmad (Author) ; Miremadi, Ghasem (Supervisor)
    Abstract
    In recent years, the use of embedded processors has grown increasingly in wide range of computer systems; so that most of manufactured CPUs are used in emebedded systems many of which are safty-critical systems such as medical devices, aircraft flight control, space systems, nuclear systems, etc. The incidence of failure in these systems can cause irreversible damages on human life, financial or environmental matters. Silicon process technology trends, such as reducing the threshold voltage, increasing the frequency and decreasing the size of transistors, not only caused increase in single-bit fault rate but also caused occurance of multi-bit faults. Due to importance ofcorrect operation of... 

    An Efficient Reconfigurable Architecture in Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Tamimi, Sajjad (Author) ; Asadi, Hossein (Supervisor)
    Abstract
    Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, Field-Programmable Gate Arrays (FPGAs) are used in industry for implementing either an entire embedded system or a Hardware Description Language (HDL)-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors. In this thesis, we present an efficient reconfigurable architecture to implement embedded processors in... 

    Value-Aware low-power register file architecture

    , Article CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 44-49 ; 9781467314824 (ISBN) Ahmadian, S. N ; Fazeli, M ; Ghalaty, N. F ; Miremadi, S. G ; Sharif University of Technology
    2012
    Abstract
    In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, "Value-Aware Partitioned Register File (VAP-RF)", employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure  

    Software-based control flow error detection and correction using branch triplication

    , Article Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, 13 July 2011 through 15 July 2011 ; July , 2011 , Pages 214-217 ; 9781457710551 (ISBN) Ghalaty, N. F ; Fazeli, M ; Rad, H. I ; Miremadi, S. G ; Sharif University of Technology
    2011
    Abstract
    Ever Increasing use of commercial off-the-shelf (COTS) processors to reduce cost and time to market in embedded systems has brought significant challenges in error detection and recovery methods employing in such systems. This paper presents a software based control flow error detection and correction technique, so called branch TMR (BTMR), suitable for use in COTS-based embedded systems. In BTMR method, each branch instruction is triplicated and a software interrupt routine is invoked to check the correctness of the branch instruction. During the execution of a program, when a branch instruction is executed, it is compared with the second redundant branch in the interrupt routine. If a... 

    ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications

    , Article Proceedings -Design, Automation and Test in Europe, DATE, 14 March 2011 through 18 March 2011 ; March , 2011 , Pages 289-292 ; 15301591 (ISSN) ; 9783981080179 (ISBN) Ebrahimi, M ; Miremadi, S. G ; Asadi, H ; Sharif University of Technology
    2011
    Abstract
    We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller circuitry to restore the system to the fault-free state. As a case study, we have implemented the proposed ScTMR technique on an embedded processor, suited for safety-critical applications. Exhaustive fault injection experiments reveal that the proposed architecture has the error detection and... 

    Robust register caching: An energy-efficient circuit-level technique to combat soft errors in embedded processors

    , Article IEEE Transactions on Device and Materials Reliability ; Volume 10, Issue 2 , February , 2010 , Pages 208-221 ; 15304388 (ISSN) Fazeli, M ; Namazi, A ; Miremadi, S. G ; Sharif University of Technology
    2010
    Abstract
    This paper presents a cost-efficient technique to jointly use circuit- and architecture-level techniques to protect an embedded processor's register file against soft errors. The basic idea behind the proposed technique is robust register caching (RRC), which creates a cache of the most vulnerable registers within the register file in a small and highly robust cache memory built from circuit-level single-event-upset-protected memory cells. To guarantee that the most vulnerable registers are always stored in the robust register cache, the average number of read operations during a register's lifetime is used as a metric to guide the cache replacement policy. A register is vulnerable to soft... 

    Power and frequency analysis for data and control independence in embedded processors

    , Article 2011 International Green Computing Conference and Workshops, IGCC 2011, 25 July 2011 through 28 July 2011 ; July , 2011 , Page(s): 1 - 6 ; 9781457712203 (ISBN) Samie, F ; Baniasadi, A ; Sharif University of Technology
    2011
    Abstract
    In this work we study control independence in embedded processors. We classify control independent instructions to data dependent and data independent and measure each group's frequency and behavior. Moreover, we study how control independent instructions impact power dissipation and resource utilization. We also investigate control independent instructions' behavior for different processors and branch predictors. Our study shows that data independent instructions account for 34% of the control independent instructions in the applications studied here. We also show that control independent instructions account for upto 12% of the processor energy and 15.6%, 11.2% and 8.6% of the instructions... 

    Performability comparison of schedulability conditions in real-time embedded systems

    , Article Proceedings - 3rd International Conference on Dependability, DEPEND 2010, 18 July 2010 through 25 July 2010, Venice, Mestre ; July , 2010 , Pages 70-75 ; 9780769540900 (ISBN) Bashiri, M ; Miremadi, S. G ; IARIA ; Sharif University of Technology
    2010
    Abstract
    In modern safety-critical real-time embedded systems, performance and reliability are two most important parameters. The joint consideration of these two parameters is called performability. This paper evaluates and compares different schedulability conditions, which are used for scheduling tasks with fault-tolerant Rate-Monotonic (RM) algorithm, with respect to their performability. The task reexecution scheme is used to implement fault tolerance in the RM scheduling algorithm. To evaluate the schedulability conditions, a software tool is developed to simulate an embedded processor with m schedulable periodic tasks. The results show that among five different schedulability conditions used... 

    Opportunities for embedded software power reductions

    , Article Canadian Conference on Electrical and Computer Engineering ; 2011 , Pages 000763-000766 ; 08407789 (ISSN) ; 9781424497898 (ISBN) Assare, O ; Goudarzi, M ; Sharif University of Technology
    2011
    Abstract
    While performance and power consumption of processors present a classic trade-off in designing embedded hardware, software can be optimized in favor of both performance and energy. We evaluate the impact of optimizations at different stages of designing embedded software. We show that algorithm choice and compiler optimizations aimed at improving performance can also reduce energy consumption of an embedded processor. We also propose energy-aware compilation guidelines which can further reduce energy consumption without performance penalties. Our experimental results show that up to 85% energy reduction and 89% performance improvement can be achieved by these techniques  

    Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors

    , Article Microelectronics Reliability ; Volume 51, Issue 12 , December , 2011 , Pages 2374-2387 ; 00262714 (ISSN) Fazeli, M ; Namazi, A ; Miremadi, S. G ; Haghdoost, A ; Sharif University of Technology
    2011
    Abstract
    This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the... 

    Memory mapped SPM: Protecting instruction scratchpad memory in embedded systems against soft errors

    , Article Proceedings - 9th European Dependable Computing Conference, EDCC 2012 ; 2012 , Pages 218-226 ; 9780769546711 (ISBN) Farbeh, H ; Fazeli, M ; Khosravi, F ; Miremadi, S. G ; Sharif University of Technology
    IEEE  2012
    Abstract
    Predictability, energy consumption, area and reliability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories play an increasing role to satisfy these concerns. Both cache and SPM as on-chip SRAM memories are highly vulnerable to soft errors and as they contain the most frequently used blocks of the program, their errors can easily propagate in system leading to erroneous results. Unlike the instruction cache, an error in the instruction SPM cannot be corrected using only parity bits by invalidating the erroneous line. This study suggests a low-cost mechanism to protect the instruction SPM against soft errors. The main idea underlying the...