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Low-power Design of Decimal Multipliers
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Ali Reza (Supervisor)
Abstract
Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require their data to be precise while binary number system cannot ensure precision. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today’s digital systems. Hence, in this thesis we present a comparative study of parallel decimal multipliers, considering energy/power consumption (leakage and dynamic power consumption), latency and area. Furthermore, we present two novel techniques to reduce energy/power consumption of...
CNTFET full-adders for energy-efficient arithmetic applications
, Article 6th International Conference on Computing, Communications and Networking Technologies, 13 July 2015 through 15 July 2015 ; 2015 ; 9781479979844 (ISBN) ; Hashemi, M ; Haghshenas, K ; Rezaee, S ; Rapolu, S ; Nikoubin, T ; University of North Texas ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm...
A low cost circuit level fault detection technique to full adder design
, Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011, Beirut ; 2011 , Pages 446-450 ; 9781457718458 (ISBN) ; Fazeli, M ; Hessabi, S ; Miremadi, S. G ; Sharif University of Technology
2011
Abstract
This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition
Sub-threshold charge recovery circuits
, Article Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 3 October 2010 through 6 October 2010, Amsterdam ; 2010 , Pages 138-144 ; 10636404 (ISSN) ; 9781424489350 (ISBN) ; Mohammadi, H. G ; Ejlali, A ; IEEE; IEEE Circuits and Systems Society; IEEE Computer Society; HiPEAC Compilation Architecture ; Sharif University of Technology
2010
Abstract
Embedded systems account for wide range of applications. However, the design of such systems is faced with a diverse spectrum of criteria. The energy consumption, performance, and demanding security concerns are some of the most significant challenges in designing of such systems. With these challenges, the design process can be managed more easily if a flexible logic circuit with the ability of satisfying the abovementioned concerns is taken into account. To achieve such a logic circuit, in this paper we have combined the sub-threshold operation and charge recovery techniques. Using our technique, lower power consumption, ability of operating at higher frequencies, and more security (to...