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    Improving Performance and Power Consumption of Optical CMPs Using Inter-core Communication Prediction

    , M.Sc. Thesis Sharif University of Technology Ghane, Millad (Author) ; Sarbazi Azad, Hamid (Supervisor)
    Abstract
    Studying data flows in conventional applications of Multi-Processor System-on-Chips (MPSoCs) denotes that most of these flows are the ones that transfer huge volume of data in inter-core communications. Previous works try to present architecture for interconnection network which some paths with low power and latency are reserved (statically or dynamically). However all of the presented methods are based on subnetworks or mechanism of transferring control messages (to establish a path and tear it down after transmission of data). Optical connections with low cost, low power and high bandwidth are good candidates to reduce power consumption of Network-on-Chips (NoCs). Therefore, using optical... 

    On Some Properties of OTIS Networks and Similar Networks

    , M.Sc. Thesis Sharif University of Technology Malekimajd, Marzieh (Author) ; Movaghar Rahimabadi, Ali (Supervisor)
    Abstract
    The plausibility of embedding cycles of different lengths in the graphs of a network (known as the pancyclicity property) has important applications in Interconnection networks, parallel processing systems, and implementation of a number of either computational or graph problems such as those used for finding storage schemes of logical data structures, layout of circuits in VLSI and etc. OTIS network is an important Interconnection network that worth investigating. This kind of network has benefits of having electronic connection and optic connection simultaneously. Furthermore, independent of the technology of network, the topology of this network has importance. In this thesis, we have... 

    A Communication Model between SIMT Cores for Improving GPU Performance

    , M.Sc. Thesis Sharif University of Technology Keshtegar, Mohammad Mahdi (Author) ; Hesabi, Shahin (Supervisor)
    Abstract
    In recent years, GPUs are becoming an ideal candidate for processing a variety of high performance applications. By relying on thousands concurrent threads in applications and the computational power of large numbers of computing units; GPGPUs have provided high performance and throughput. To achieve the potential computational power of GPGPUs in broader kinds of applications, we need to apply some modifications in their architecture. In the baseline architecture, the maximum part of chip area is devoted to SIMT cores which their communication is handled through an interconnection network and a slow off-chip memory. Recent research shows that out of many types of miss events the last level... 

    , M.Sc. Thesis Sharif University of Technology (Author) ; Sarvari, Reza (Supervisor) ; Fardmanesh, Mehdi (Supervisor)
    Abstract
    As technology scales down Integrated Circuits operates at higher frequency and lower dimensions. Interconnects inside these chips operate at gigahertz frequencies and manometer range. As mean free path of electrons become comparable with wire dimensions and skin depth, first one will result in Size Effect and second one will result in Anomalous Skin Effect. In this thesis we are trying to characterize these effects. The MFP of electron for copper at room temperature is about 38nm and therefore neither Size effect nor ASE are measurable at room temperature with our available equipment. Hence, the idea is to measure ASE for copper wires at liquid nitrogen temperature (77K). We showed that ASE... 

    Optimal Multi-Level Interconnect Architecture for GSI Using Novel Solutions Replacing Copper

    , Ph.D. Dissertation Sharif University of Technology Kishani Farahani, Esmat (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    Although a lot of research has been done on Carbon-based interconnect, there are many important questions unanswered. For example, there is no compact model for the resistance of bundle of CNTs at high frequencies, at which interconnects will be operating due to the scaling. Also there are many studies comparing CNT, GNR, and Cu wires but there is no study to show how much this will impact the design of a chip at today’s Giga Scale Integration. This comprehensive study should include chip performance, power dissipation and total number of metal levels. These two big questions are investigated in this dissertation. In the first part, high frequency behavior of CNT bundles is studied. A... 

    Analyzing the Effect of Interconnection Topology on the Performance of Enterprise SSDs

    , M.Sc. Thesis Sharif University of Technology Soltani, Behnaz (Author) ; Sarbazi-Azad, Hamid (Supervisor) ; Hesabi, Shahin (Co-Advisor)
    Abstract
    In recent years, flash-based Solid State Drives (SSDs), because of their lower power consumption, higher throughput, and resistance against physical damages compared to Hard Disk Drives (HDDs) have confronted ever increasing usage in data center, cloud applications, and enterprise servers. Recently, advantages of using interconnection networks between SSD controller and NAND Flash chips for transferring data and commands have been shown. Interconnection network intrinsically provides many advantages such as maintaining the signal integrity at high frequencies, pipelining support, sharing the communication resources, eliminating communication bottlenecks, and reducing power consumption. The... 

    Flash Aware Analytical Modeling of SSDs Interconnection Networks

    , M.Sc. Thesis Sharif University of Technology Masrour, Fatemeh (Author) ; Sarbazi Azad, Hamid (Supervisor)
    Abstract
    In recent years applying solid state drives in data centers, cloud computing infrastructures and commercial servers have had a considerable growth. Low power consumption, high throughput and resistance to physical damages are some of the advantages of SSDs over HDDs. In recent works the necessity of using an interconnection network as a communication subcomponent between memory flash chips and disk controller is described. Disk mechanisms (mapping, wear-leveling and garbage collection) influence on throughput of the network. Based on this fact in this research an analytical model is provided considering disk mechanisms, flash chip structure and traffic characteristics. The error of the model... 

    NumericalModel for Surface Scattering and Grain Boundary Scattering of Metallic Wires

    , M.Sc. Thesis Sharif University of Technology Abbaspour, Elhame (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    Recently, the size of copper interconnects is going to reach lower than the mean free path of electrons for copper. In this situation, we should consider the effect of other scattering mechanisms as well as thermal scattering on copper thin films. In this work we study both DC size effect and anomalous skin effect on resistivity by a Monte Carlo method. Contribution of each scattering mechanism and the interaction between them are analyzed separately. The structure of electrical field and distribution of current in thin films have also been studied. Investigating of the effect of exact nature of surface scattering and grain boundary scattering on resistivity is one of the interests of this... 

    On Some Pancyclicity Properties of OTIS Network

    , M.Sc. Thesis Sharif University of Technology Shafiei, Tayebeh (Author) ; Movaghar, Ali (Supervisor)
    Abstract
    A parallel computer system is composed of a collection of processors used to speed up running a program or performance of multiple programs. If we consider the processors as nodes and the channels between processors as edges, the constructed graph represents an interconnection networks. Network topology affects performance and energy consumption of interconnection network very much. Some parameters of topology quality are low node degree and diameter, high connectivity degree and bisection width and symmetry. Since some of these parameters are in contrast with others, a network with more parameter improvements, is more desirable. Finding cycles with specific length and particularly ... 

    Entropy Analysis and its Application in Interconnection

    , M.Sc. Thesis Sharif University of Technology Soltanian, Abbas (Author) ; Baniasadi, Amir Ali (Supervisor)
    Abstract
    Reducing interconnection costs on chip and power consumption are important issues in designing processors. In a processor, a significant amount of total chip power is consumed in the interconnection. The goal of this research is to find a way to reduce power consumption in the interconnection. In this project we propose a new data sending method in which an LZW-like compression algorithm is exploited to compress data before sending it over the interconnection. Then, the codes of the compressed data are sent through the interconnection in order to reduce the number of dynamic cycles. The simulation results show that using this method can reduce 52% of dynamic power consumption  

    Design and Implementation of Local Interconnect Network (LIN)Transceiver in High Voltage BCD 0.18 um

    , M.Sc. Thesis Sharif University of Technology Maghbouli, Mahsa (Author) ; Medi, Ali (Supervisor) ; Faez, Ramin (Supervisor)
    Abstract
    In this study, a Local Interconnect Network (LIN) transceiver was designed and implemented. This chip contains transmitter, receiver, low power receiver, digital control unit, oscillator, voltage regulator, high voltage switch, temperature sensor and battery voltage detector. The main focus on this study was on designing transmitter,receiver, low power receiver and temperature sensor. Through designing of this chip, in addition to functional and physical layer specification that mentioned in ISO 17987, electromagnetic compatibility specifications have been considered significantly.The designed chip with slope control and wave shaping of BUS signal has excellent radiated emission performance.... 

    All-Optical Scalable Multi-stage Interconnection Network for Data Centers

    , M.Sc. Thesis Sharif University of Technology Movahederad, Mahdieh (Author) ; Koohi, Somayeh (Supervisor)
    Abstract
    According to the increasing amount of data exchanged among data centers, the need for speeding up and bandwidth and reduced power consumption has been increased. The information show that about 77% of the data is moved into the data centers. On the other hand, 10% of data center’s power consumption is used to data transmission. Improving the interconnection network of data centers can play an important role in reducing power consumption and speeding up. In recent years, optical interconnects have gained attention as a promising solution. Nevertheless, offering an all-optical and efficient architecture is an important issue. In this study, we intend to provide a multi-stage, all-optical... 

    All Optical Reconfigurable Network for Data Centers

    , Ph.D. Dissertation Sharif University of Technology Khani, Elham (Author) ; Hessabi, Shaahin (Supervisor) ; Koohi, Somayyeh (Supervisor)
    Abstract
    The ever-expanding growth of internet traffic enforces deployment of massive Data Center Networks (DCNs) supporting high performance communications. Optical switching is being studied as a promising approach to fulfill the surging requirements of large scale data centers. Data center networks include hundreds of thousands of nodes that require flexible, high bandwidth, and low power infrastructures for their communications. Optical interconnection networks supply the required bandwidth, consuming much lower power compared to their electrical counterparts. The heterogeneous nature of data centers’ traffic needs a flexible network architecture which can be dynamically configured according to... 

    Design for scalability in enterprise SSDs

    , Article Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT ; 24-27 August , 2014 , p. 417-429 ; ISSN: 1089795X ; ISBN: 9781450328098 Tavakkol, A ; Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    Solid State Drives (SSDs) have recently emerged as a high speed random access alternative to classical magnetic disks. To date, SSD designs have been largely based on multi-channel bus architecture that confronts serious scalability problems in high-end enterprise SSDs with dozens of flash memory chips and a gigabyte host interface. This forces the community to rapidly change the bus-based inter-flash standards to respond to ever increasing application demands. In this paper, we first give a deep look at how different flash parameters and SSD internal designs affect the actual performance and scalability of the conventional architecture. Our experiments show that SSD performance improvement... 

    Task migration in three-dimensional meshes

    , Article Journal of Supercomputing ; Vol. 56, issue. 3 , 2011 , p. 328-352 ; ISSN: 09208542 Bargi, A ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    As a result of the emerging use of mesh-based multicomputers (and recently mesh-based multiprocessor systems-on-chip), issues related to processor management have attracted much attention. In a mesh-based multiprocessor, after repeated submesh allocations and de-allocations, the system network may be fragmented, i.e. there might be unallocated nodes in the network. As a result, in a system with contiguous processor allocation, no new tasks can start running due to the lack of enough free adjacent processors to form a suitable submesh. Although there might be enough free processors available, they remain idle until the allocator can find a set of adjacent free nodes forming a submesh to be... 

    On the topological properties of grid-based interconnection networks: Surface area and volume of radial spheres

    , Article Computer Journal ; Vol. 54, issue. 5 , 2011 , p. 726-737 ; ISSN: 00104620 Sarbazi-Azad, H ; Khonsari, A ; Ould-Khaoua, M ; Sharif University of Technology
    Abstract
    Grid-based networks (or grids for short), such as meshes and tori, have been the underlying topology for many multicomputers, and have been extensively studied in the past as a graph topology. In this paper, we investigate some topological properties of grids without boundary wrap-around (meshes) and with boundary wrap-around (tori). In particular, we study the problem of finding the number of nodes located at/within a given distance from a given node (surface area/volume) in the network and derive some expressions for computing such a number. Furthermore, we provide similar expressions that improve on previous results already reported in the literature for some special cases of grids,... 

    On pancyclicity properties of OTIS-mesh

    , Article Information Processing Letters ; Vol. 111, issue. 8 , 2011 , p. 353-359 ; ISSN: 00200190 Shafiei, T ; Hoseiny-Farahabady, M.R ; Movaghar, A ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    In optoelectronic OTIS multicomputer networks (also known as Swapped networks), electrical and optical interconnects are used for local and global communication, respectively. An interesting instance of the OTIS multicomputers is the OTIS-mesh. Pancyclicity is of great importance in the implementation of a variety of parallel algorithms in multicomputers. This paper addresses the Pancyclicity problem of OTIS-mesh. More precisely, we prove that if the factor graph G of an OTIS network is a 2-D or 3-D mesh with at least one even radix, OTIS-G can embed any cycle of length l, l?{4,6,7,8,9,...,|G|2}  

    Performance modeling of Cartesian product networks

    , Article Journal of Parallel and Distributed Computing ; Vol. 71, issue. 1 , 2011 , p. 105-113 ; ISSN: 07437315 Moraveji, R ; Sarbazi-Azad, H ; Zomaya, A.Y ; Sharif University of Technology
    Abstract
    This paper presents a comprehensive performance model for fully adaptive routing in wormhole-switched Cartesian product networks. Besides the generality of the model which makes it suitable to be used for any product graph, experimental (simulation) results show that the proposed model exhibits high accuracy even in heavy traffic and saturation region, where other models have severe problems to predict the performance of the network. Most popular interconnection network can be defined as a Cartesian product of two or more networks including the mesh, hypercube, and torus networks. Torus and mesh networks are the most popular topologies used in recent supercomputing parallel machines. They... 

    Performance modeling of n-dimensional mesh networks

    , Article Performance Evaluation ; Vol. 67, issue. 12 , 2010 , p. 1304-1323 ; ISSN: 01665316 Rajabzadeh, P ; Sarbazi-Azad, H ; Zarandi, H.-R ; Khodaie, E ; Hashemi-Najafabadi, H ; Ould-Khaoua, M ; Sharif University of Technology
    Abstract
    Mesh-based interconnection networks are the most popular inter-processor communication infrastructures used in current parallel supercomputers. Although many analytical models of n-D torus interconnection networks have been reported in the literature over the last decade, few analytical models have been proposed for the 2-D mesh case (and not for the general n-D mesh network) using inaccurate approximations as they have not fully incorporated the asymmetry effects of the mesh topology, in order to reduce the model complexity. There has not been reported, to the best of our knowledge, a performance model that can deal with the n-D mesh network. To fill this gap, in this paper, we propose the... 

    Properties of a hierarchical network based on the star graph

    , Article Information Sciences ; Vol. 180, issue. 14 , 2010 , p. 2802-2813 ; ISSN: 00200255 Imani, N ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    This paper introduces a new class of interconnection networks named star-pyramid. An n-level star-pyramid is formed by piling up star graphs of dimensions 1 to n in a hierarchy, connecting any node in each i-dimensional star, 1 < i ? n, to a node in the (i - 1)-dimensional star whose index is reached by removing the i symbol from the index of the former node in the i-dimensional star graph. Having extracted the properties of the new topology, featuring topological properties, a minimal routing algorithm, a simple but efficient broadcast algorithm, Hamiltonicity and pancyclicity, we then compare the network properties of the proposed topology and the well-known pyramid topology. We show that...