Sharif Digital Repository

Size and number of high-performance data centers are fast growing all over the world in recent years. The growth in the leakage power consumption of servers along with its exponential dependency on the ever increasing process variation in nanometer technologies have made it inevitable to move toward variation-aware power reduction strategies. In this thesis, we simultaneously apply thermal- and variation-aware server placement and chassis consolidation methods to reduce total power consumption of data centers. We introduce two server placement heuristics as well as an Integer Linear Programming (ILP)-based server placement method based on power consumption of each server and the data center... 

The Technology scaling and reduction of the size of transistors has led to an increase in the switching speed and, as a result, to an increase in the clock frequency.But in recent years, the continuation of this process of increasing the clock frequency has been almost stopped considering the considerations of power consumption. Previous research has shown that approximately 30-50% of the dynamic power consumed by the microprocessor is wasted in the clock distribution network.Therefore, the design of clock distribution networks is a big challenge for future microprocessors due to the trend of Technology scaling and process variation. In this thesis, we used the emerging technology of... 

Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most affected modules by NBTI. Variations in duty Cycles and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and distributes... 

Advances in semiconductor manufacturing technologies have enabled us to build billions of transistors on a single die. However, the increasing amount of process variation in nanometer technologies has made it inevitable to move toward statistical analysis methods, instead of deterministic worst-case-based techniques, at all design levels. In this project, we studied the problem of variation-aware task scheduling for MPSoCs. To this end, we first proposed a variability analysis framework to analyze the effect of process variation on the main parameters of MPSoCs. Then, to solve the MPSoC task scheduling problem, we proposed two metaheuristic variation-aware task scheduling method based on... 

Voltage Controlled Oscillator (VCO) is one of the essential blocks in communication transceivers. The important specifications of the VCOs like Phase Noise, always is a motivation for researchers in order to introduce novel approaches to conquer these challenges. By development of technology and appearance of new fabrication technologies, this issue take more attention that the past. Also the out of control parameters like process variation and temperature, affect that. So, according to the challenges ahead and the demand of transceiver systems for low phase noise and reasonable power consumption, solutions for overcome these challenges. Finally, a class-C VCO with the tuning range of 4.25-5... 

In nanometer technologies, the effect of process variation is observed in Multi-Processor System on Chip (MPSoC) in terms of variation in processors‟ frequency and leakage power. Traditionally, only worst case values of the system parameters were concerned and a worst-case optimization algorithm was employed for an application under design. As previous researches have shown these algorithms are not optimal in terms of parametric yield compared with newly employed statistical optimization algorithms. In this project, we have considered the problem of simultaneously selecting MPSoC architecture (which includes type and number of processors and the communication media) and task and... 

By scaling the technology node, leakage power and process variations emerge as the two important factors to design a chip. Static power becomes more important when the number of portable devices which spend most of the time in the idle mode is increasing.Process variations lessen performance, reliability and lead to more leakage power. To mitigate these limitations multiple devices have been proposed to displace Bulk MOSFET.Among these devices we can name FinFET and CNTFET transistors. FinFET transistors due to their superior gate control in compare to Bulk MOSFETs transistor have shown lesser short channel effects, more scalability, more I_on to I_off ratio and lesser process variations.... 

The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. One of the key strategies for reducing power consumption is reducing the supply voltage to near or below the threshold voltage of the transistor. However, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent... 

SRAM has a very wide application in different platforms including Cache Memory in Microcontrollers, etc. also SRAM is the first candidate for memory usage in every application needing High speed or static memory circuits. SRAM Cells are constructed by Minimum size transistors in each technology node and usually the newest technology nodes are used for building SRAM blocks for accommodating maximum number of SRAM Cells in a specific area. Going through smaller technology nodes, Leakage current and Process variations problem, creates serious difficulties in designing Low Power or High speed SRAM Memories and many academic and industrial works are done wishing for improvement in SRAM power... 

CMOS technology has reached two digit nanometer dimensions. This scaling trend improves performance and power consumption on the one hand, and reduces noise margin and circuits reliability on the other. Along with downscaling, sensitivity to radiation induced soft errors is increasing. As CMOS dimensions are shrinking, node capacitance of circuits become smaller. Consequently, particles with smaller charge could induce parasitic voltages in some nodes and result in soft errors. There are more particles with smaller charge than the ones with larger. Therefore, soft error rate is rapidly increasing with technology advances. Single Event Multiple Effects (SEMEs) is a new challenge emerged in... 

Nowadays the performance of multi-core systems is increasing; however, the limited off-chip bandwidth of DRAMs is the biggest limiting factor for keeping up this trend. 3D stacked memories are good alternatives for current memories as they utilize high-bandwidth low-power through silicon via (TSV) connections. The main problem of these structures is significant rise of temperature as heat cannot be dissipated easily from the middle layers. As a result, utilizing thermal and power-aware management techniques is one of the most critical design goals of these systems. DRAM manufacturers consider timing parameters of memory controller conservatively high to guarantee the true functionality of... 

Process Variation is seen as statistical variations in leakage current and delay of transistors in nano-scale technologies. The amount of process variations increase as the size of transistors decrease by technology scaling such that those effects can be seen in frequency of MPSoC (Multi-Processor System-on-Chip) cores and their leakage power deviation. These variations cause the tasks duration and power consumption fluctuate in different processors in an MPSoC instance. Consequently, some chip instances of the same MPSoC may consume more time and power than their considered limitations. Hence considering the process variation is necessary and required for MPSoC optimization at different... 

Developing to the sub-micron dimentions reduces the size of integrated circuits, so interconnects and a variations in their characteristics has more effects on circuit performance. Worst case study is the most common method in these systems, but in many cases interconnect lines are independent from eachother. Analysis state that worst case is out of the distribution in many cases (with zero possibility) and result in a pessimistic design. Statistical analysis should replace worst case analysis in multi varient systems. In this titile, statistical analysis will be used to investigate performance of interconnects in new technology. Maximum variation in interconnect parameters are considered...