Sharif Digital Repository

High speed data converter are very often used in telecommunication systems. Since these systems are increasingly used in mobile foem reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate 200MS/s with a power consumption of 35 mW for the input level of 1Vp-p and a 1.8V power supply in 0.18um CMOS technology.
To reach these goals, a number of low power techniqes are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors is optimized analytically which leads to simple back-envelope formulas to calculate the optimum values. In circuit level, a... 

Increasing demand for high-speed and high-resolution ADCs as much as low-power ones and on the other hand, the obstacles in the way of reaching them make calibration and compensation methods more significant for obtaining ADCs with the better specs. Among the cases which need modification, the modification of C-2C-based SAR ADCs, which can decrease the power significantly, and the modification of time-skew error of time-interleaved ADCs, which is the main and the most challenging error in this type of ADCs, could be the two of the effective ways to making the State-of-the-Art ADCs. In this project for the first time, a novel compensation method for C-2C parasitic charges is proposed which... 

SAR ADC is a data converter which is based on binary search to convert an analog signal to a digital signal. Unlike other converters like pipeline, most of its constituent parts are digital, and hence scalable with process and consume less power, moreover can have better speed and power performance. With advanced technologies, namely 45nm and 32 nm CMOS, SAR ADCs are preferable as they consume much less power and area, therefore well-suited for portable applications, as opposed to Flash and Pipleline converters.
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a... 

Low power and high speed analog-to-digital converters (ADCs) are the key elements of communication and computing systems. There are several ADC structures such as delta-sigma, flash, pipeline, and successive approximation register (SAR) for different applications, albeit SAR ADCs are natural candidates of onchip designs for their low power and scalability benefits. Nowadays, SAR ADCs are widely being used in low-power moderate-resolution applications which need several tens of MS/s to low GS/s sampling rates. By virtue of the technology scaling power consumption of digital parts of a SAR ADC is reduced significantly. As a result, in a SAR ADC the power consumption of the digital-to-analog... 

ADC is one of the key functional blocks of any mixed signal system and therefore must be optimally designed concerning power, performance, resolution and silicon area. Among different architectures have been employed up to now, successive approximation register ADCs are known as the ones with lower power, more simplicity and lower sampling rate. Benefiting from scaling down the CMOS technology results in higher sampling rate and lower power SAR ADCs replacing other types of ADCs. To achieve the desired ADC performance, efforts are usually focused on the improvement of circuit techniques as well as on the introduction of new or combinational architectures based on SAR ADCs. This thesis aims... 

Effect of resolution of Time to Digital Converters (TDCs) on the performance of All-Digital Phase Locked Loops (ADPLLs) and capability of achieving higher resolution in advanced technologies lead to introducing different kinds of TDCs. Beside the analysis of different kinds of TDCs, This thesis proposes three new TDCs based on the time amplifi-cation concept. A new pipeline TDC is designed using a wide dynamic range time amplifi-er. A new method is used to widen dynamic range of the conventional time amplifiers. In order to get a low power high resolution conversion, a new delay element design is devel-oped to reduce the delay value and its sensitivity to mismatch and process variations.... 

Increasing demand for digital systems has led to developing signal processing in the digital domain. For this purpose, Analog to Digital Converters is used to convert analog signals to digital ones. Apart from that, by decreasing the size of transistors, it has been possible to implement the system on a chip that needs communication between analog and digital signals. The designed converter in this project is suitable for instrumentation purposes and especially for use in the control loop of a DC­DC digitally voltage converter. ADC architectures are mainly classified into two groups attributed with high bandwidth or with high resolution. Nature of on­chip measurement requires high... 

Converting analog signal to digital one is one of the most important issues in signal processing which can be done by using analog to digital converter (A/D). In the first part of this thesis, sigma delta converters based on minimum support filter are investigated. Then, we will show that iterative algorithm can be used in order to improve the performance of the overall system significantly. Asynchronous converters can be utilized for the sake of decreasing power in the process of analog to digital converting. In these converters, a few numbers of samples will be taken from the regions which signal has high autocorrelation. In other words, samples in the asynchronous converters have more... 

Delta-Sigma Analog-to-Digital converters have been positioned themselves as robust reliable converters so far. The magic Of extracting high resolutions from low bit ADC has made them popular between designers. Previously, the noise-shaping magic was used in high-resolution applications such as high-quality audio signal converters. However, as the technology scales and proceeds, these converters are approaching RF applications, too. Power and OSR trade-off limits this progress. To increase OSR in bandpass delta-sigma modulators, more power should be consumed to increase the quality factor of loop filters. In this thesis, a systematic approach has been utilized. An n-path filter is employed... 

The successive approximation digital to analog converters are appropriate selection for use in new technologies and low-powered applications. Despite the low power consumption of this kind of converters, there are some applications like medical which require very low power consumption. In order to reduce the power consumption of SAR ADC, capacitive digital to analog converters and comparators are great importance. In this Thesis, monotonic switching method has been used, the switching power of this method is lower than the conventional method by 81.2%. Since the common mode of the output of this type of switch is variable, the offset is sensitive and requires a technique to resolve this... 

Massive MIMO is a key enabling technology in the fifth generation (5G) wireless communication systems. In this technology, the base station is equipped with a large number of antennas (e.g. 100-200) and communicates with a relatively smaller number of user terminals. The large number of antennas at the base station, on one hand, has enabled unprecedented improvements in data rate and energy-efficiency, while on the other hand has posed challenges on the practical deployment of this technology.One of these challenges, is the high computational complexity of the baseband processing algorithms, such as precoding, due to the large number of antennas. In this research, we propose a novel ZF... 

The digital nature of Successive Approximation Register (SAR) Analog to Digital Converter (ADC) suits them for the new technologies with small gate length and low power applications. Applications such as ultra-wideband receivers, satellite receivers and high speed serial links demand medium resolution and high sampling rate ADCs. Due to binary search algorithm speed limitations, SAR ADCs belong to low to moderate speed category. In this thesis time-interleaving and two-bit-per-cycle technique are used in order to increase SAR ADC sampling rate. These techniques are both sensitive to offset and if the comparators used in SAR ADC have different offsets signal-to-noise-and-distortion will be... 

Phase noise is one of the important parameters in telecommunication systems and its measurement has always been considered. Digital phase noise measurement methods have a simpler implementation and calibration than analog types. Also, in digital methods, amplitude noise and phase noise can be separated and measured both at the same time. Comparing the phase noise of two oscillators with different frequencies is another major advantage of digital methods. The sensitivity of digital methods is limited to the noise of their analog-to-digital converters. Cross-correlation technique is used to reduce the minimum measurable level of phase noise. This method reduces the internal noise of the... 

Analog to digital converters with different specifications are widely used in modern electronic circuits. The significant demand on pipeline converters in several low power applications is mainly due to their high speed and high resolution characteristics. Fast and simple design of analog circuits using CAD tools, is highly sought after by integrated circuit designers. In this thesis, pipeline analog to digital converters is studied and a CAD tool is proposed for transistor level design and optimizations. The main advantage of this design in comparison with the previous works is that the yield and power consumption are considered as optimization factors. The module operates in three parts:... 

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) converts an analog signal to a digital code based on binary search. In contrast to other converters, such as Pipeline and Flash ADCs, most of the SAR ADC components are digital, hence, SAR ADC is technology scalable. Therefore, designed using smaller tehcnologies, SAR ADCs are able to operate at a higher frequency with a lower power consumption and area. The main focus of this thesis is to reduce power consumption, although the proposed techniques and circuits are able to improve other features such as precision, area, or speed.Considering Digital to Analog Converter (DAC), a low-power structure and a novel method to...