Sharif Digital Repository

In this paper, application of a capacitive sensor system in recording small displacements is discussed. Through using a simple transducer and a monitoring circuit, change in capacitance has been detected as a function of the capacitor air-gap distance. There is a linear relation between gap distance and output of a sensor for a wide gap range of 0.5 to 5 mm. The reported system provides means for measuring displacements up to 5 mm with a resolution better than 250 nm. By decreasing the dynamic range of the transducer to 250 μm, a small displacement of the order of 100 nm is detectable. With the present system, a minimum displacement of about 200 nm (200 ppm) for the gap distance of 1 mm is... 

This paper proposes a novel, one-part, variable capacitor, using semi-conducting carbon nanotube (CNT). This variable capacitor works based on the change in the electronic structure of CNTs under applied voltage and deformations. Positive and negative charges are stored at both ends of a non-zero band gap nanotube which works as metallic electrodes in parallel plate capacitors. Also the neutral strip in the middle acts as the dielectric part of a conventional capacitor under the influence of an external electric field. Mechanical strains on carbon nanotube change its band gap energy and thus the length of neutral strip and charged regions. The lengths of these parts are primarily dependent... 

A compact, low power, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5um CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature we variations. For this purpose, an accurate delayed clock is generated. structure besides MOSFET capacitors offers a impact and low power circuit. The area of the circuit is 0.08mm2 while consumes 380uArms SV power supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from... 

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed... 

Here, a solvothermal method for synthesis of porous Ni–Co binary oxide (NiCo2O4) nanorods followed by thermal decomposition is described. The prepared nanorods were characterized by X-ray diffraction (XRD), scanning electron microscopy (SEM), and Brunauer Emmett Teller (BET) methods. These porous NiCo2O4 nanostructures were promising candidates in the development of high capacity supercapacitors and having excellent cycling performance due to high specific surface area. In addition, the influence of annealing rate on the structure and electrochemical behavior of the synthesized nanorods was investigated. The results showed that the annealing rate had a direct effect on the crystalline... 

This article indicates the accurate method for load level calculation to solve the power flow problem when capacitor reactive power is involved. Using the correct method causes some changes in the results and conclusion stated in the discussed paper on optimal reconfiguration and capacitor placement in radial distribution systems  

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

A space vector modulation (SVM) approach is proposed to control a four-switch rectifier with power factor correction and compensating the effect of capacitors voltage ripple. The theory and performance of this method are presented, and the method effectiveness is demonstrated by extensive simulations. The simulation results show that the capacitor voltage ripple effects in the output voltage and current shaping can be omitted and the rectifier can work agreeably under high power factor condition although capacitors voltage is not balance. The allowable amount of this unbalanced value of filter capacitors is determined  

A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching... 

Up to now, multifunctional varistor-capacitor materials were based on TiO2, even though these materials failed to have practical applications. For the first time, in this research, multifunctional varistor-capacitor properties are observed in the CuO-doped SnO2-CoO-Sb2O3 system. The XRD analysis showed that this system has a single phase microstructure. SEM images indicated that the CuO addition resulted in a better densification and larger grain size. The very low electric breakdown field of the CuO-doped SnO2-CoO-Sb2O3 system (12 V/mm, similar to TiO2), is a consequence of coarse-grained microstructure. This varistor had a suitable surge withstand capability as well. The colossal... 

In this paper, an analytic model of the energy consumption of the Stepwise Adiabatic Circuits (SAC) when it is possible to discharge the load capacitor is proposed. Using this model, analytical derivations are calculated which shows us the power saving of the SACs. Using analytical derivations, the sizing of a capacitor tank is determined for a desired energy saving. For example, the derivations predict that if the sizing of the 3-step series tank capacitors is equal to the load capacitor, the power saving is 55%. Also, if the sizing of the tank is very large the energy saving of a 3-step stepwise charging is equal to 66.7%. Several Simulations in 0.18μm CMOS technology prove the accuracy of... 

Due to the important role that distribution systems play in quality of power delivered to the customers, there has always been a great deal of interest in investigating different methods of efficiency enhancement for these networks. Two of these methods are Feeder Reconfiguration (FR) and Capacitor Allocation (CA); both have been widely employed to reduce losses and improve several other operational characteristics in electrical power distribution systems. As in FR process the topology of the network changes, it is necessary to change some previous settings; for instance: the capacity of capacitor banks in service in each bus, after each reconfiguration process. This is due to the fact that... 

Improvement in switching techniques is one of the effective methods for increasing the voltage quality in Multilevel Inverters. In this paper, a novel switching technique using frequency modulation is proposed to achieve high quality output voltage of multilevel inverters. This method is employed to different configurations of multilevel inverters consist of Diode Clamped (or Neutral Point Clamped), Flying Capacitor and Cascaded H-bridge. Each multilevel inverter which utilizes this technique is modeled and simulated to investigate the performance of this method by the help of MATLAB/Simulink software. The Results show that this innovative method considerably reduces total harmonic... 

This paper applies different approaches to solve network reconfiguration and capacitor placement/setting problem. First, reconfiguration and capacitor placement is solved for power loss minimization. Second, medium and long-term planning perspective is considered for the problem which takes into account reliability cost in addition to energy losses cost. A heuristic algorithm is used in this study for reliability evaluation considering protection schemes and isolation points in the distribution network. The problems are solved by Harmony Search Algorithm, and it is shown that its performance is much more satisfactory than several other metaheuristic algorithms to solve reconfiguration and... 

A new switching method for the stabilisation of a one-dimensional capacitor array tank for the stepwise charging of a load capacitor is presented. In this method, the tank capacitor configuration is rearranged in a circular manner once the charging process of a load capacitor finishes and before the charging process of a new load capacitor begins. Unlike previously reported methods, this method does not require backward switching for the stabilisation of tank capacitor voltages. Hence, the proposed method reduces the number of charging process steps by a factor of up to 2 compared with the conventional method. Moreover, since the tank recycles its charge inherently, the capacitive load can... 

In this paper a theoretical comparison between the performance of switched-capacitor (SC) and switched-current (SI) pipeline analog-to-digital converters (ADCs) is presented. Power dissipation and die area of SC and SI implementations are compared based on linearity and noise constraints. It is shown that if nonlinearity errors of the class AB SI ADCs are removed by calibration, their performance prevails that of the SC ADCs. Also it is shown that class AB SI ADCs occupy less die area than SC ADCs for a given resolution. © 2007 IEEE  

Performance enhancement of supercapacitors has been recently discussed. In this paper a novel and facile procedure for functionalization of graphene with some electroactive molecules is presented. The graphene has been functionalized by catechol-based molecules, which are electroactive molecules with electrochemically reversible properties. The functionalized graphene exhibits very effective pseudocapacitor behaviorfor charge storage. For the first time, with the aim of an electrosynthesis procedure, catechol is covalently attached on graphene sheets. This attachment has been investigated by electrochemical, X-ray photoelectron spectroscopy and attenuated total reflectance methods. Catechol... 

This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW  

In practice, some differences are usually observed between computer simulation and experimental results of a chaotic circuit. In this paper, it is tried to obtain computer simulation results having more correlation with those obtained in practice by using more realistic models for chaotic circuits. This goal is achieved by considering the fractionality nature of electrical capacitors in the model of a chaotic circuit  

An efficient layout technique is proposed to eliminate the effect of the bottom-plate capacitors in a C-2C Digital to Analog Converter (DAC). Using this technique, the bottom-plate capacitors of 2C capacitors in the C-2C structure are placed in parallel with 1C capacitors. Then, the effect of the bottom plate capacitors is nulled by modifying the size of the main 1C capacitors. Hence, avoiding the complexity of calibration, this technique can preclude the effect of the bottom-plate to ground capacitance. Statistical simulations prove that the proposed technique is robust to non-ideal effects such as mismatch or parasitic capacitors. A 10-bit C-2C DAC is modeled in COMSOL Multiphysics using...