Sharif Digital Repository

To get a more accurate model for the simulation of single electron transistors (SETs), we propose a new macro-model that includes an electron tunneling time calculation. In our proposed model, we have modified the previous models and have applied some basic corrections to the formulas. In addition, we have added a switched capacitor circuit, as a quantizer, to calculate the electron tunneling time. We used HSPICE for a high-speed simulation and observed that the simulation results obtained from our model match more closely with that of SIMON 2.0. We also could evaluate the time of electron tunneling through the barrier by using the quantizer. Clearly, our macro-model gives more accurate... 

Often, during fabrication processes of fiber-matrix composites, the pertinent interface may be made imperfectly bonded either deliberately or undesirably. The effect of electric capacitors and mechanical imperfections on the electro-mechanical fields associated with an anisotropic piezoelectric matrix containing a cylindrical inhomogeneity made of a different anisotropic piezoelectric material is of interest. In fact the interface imperfection condition presented in this paper is quite general, in the sense that any combination of mechanical and electrical imperfections may exist. The interface electrical imperfection is mimicked by the electric capacitors. The capacity of the capacitors is... 

In this paper a new technique called switched-resistor is used as an alternative to switched-capacitor circuits in a low-voltage low-power high-speed A/D converter. Simulation results for an 8-bit 150MS/s pipeline ADC are presented. This converter consumes 20mW from a 1.8V supply and provides an ENOB of 7.5bit. © 2007 IEEE  

A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 μm mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1 % over a... 

In this paper, a compact algorithm for balancing the load and correction of power factor in three-phase three-wire system is presented. Susceptances of SVC in each phase are computed as a function of real and imaginary parts of line current. This calculation is based on unity power factor and elimination of negative sequence of currents. A laboratory prototype of Thyristor Switched Capacitor (TSC) at 380V and 45KVAR is designed and implemented. Also, a new approach for measuring active and reactive power, power factor and voltage is presented. This measuring technique is based on integration of current signal over a specific part of voltage signal period. Finally, a brief description of... 

This paper presents a broad-band bandpass filter (BPF) designed as a channel-select filter for wireless applications. It is implemented as a low-pass filter (LPF) in series with a high-pass filter (HPF) for lower power consumption compared to true BPF. Semiscaling of the filter nodes is superior in the wireless receiver over traditional full scaling. The HPF is built with low-pass feedback of an amplifier. The bandwidth is selectable from 625 kHz, 2.5 MHz, or 10 MHz. The filter stopband loss is more than 50 dB extending beyond 100 MHz, and passband ripple less than 2.5 dB. Fabricated in a 0.6-μm CMOS process, it provides a minimum input noise of 16 nV/√Hz noise with 22.5-dBm out-of-band... 

In this paper, an accurate fault location algorithm for series compensated power transmission lines is presented. A distributed time domain model is used for modeling of the transmission lines. The algorithm makes use of two subroutines for estimation of the fault distance-one for faults behind the series capacitors and another one for faults in front of the series capacitors. Then a special procedure to select the correct solution is utilized. Samples of voltages and currents at both ends of the line are taken synchronously and used to calculate the location of the fault. The proposed algorithm is independent of fault resistance and does not require any knowledge of source impedance. The... 

A new method for modelling and analysis of non-linearity errors caused by the capacitor mismatches and op-amp non-idealities in two-step analogue-to-digital converters (ADCs) is presented. Analytical formulas for estimation of the ADC integral non-linearity (INL) are derived. Using the proposed method, the ADC INL can be calculated in terms of the capacitor mismatches standard deviations. Therefore time-consuming Monte Carlo simulations which are conventionally used to evaluate the effect of random capacitor mismatches on the ADC linearity can be avoided. The effect of op-amp non-idealities, which are frequently examined by the circuit-level simulations, can also be evaluated using the... 

This paper deals with realization of fractional-order impedance functions by passive electrical networks composed of a fractional capacitor and some RLC components. The necessary and sufficient conditions for the existence of such a realization are found in a general case. Also for impedance functions described by a class of fractional-order transfer functions, the realizability conditions are stated as some algebraic conditions on the parameters of the transfer function. Moreover, a procedure is proposed for implementation of such impedance functions by passive electrical networks composed of a fractional capacitor and some RLC components. Numerical examples are presented to show the... 

Thermal noise is one of the most important limiting factors on the performance of switched-capacitor (SC) circuit due to the aliasing effect of wide-band thermal noise. In this paper a new simple method for estimating the effect of thermal noise is presented. In the proposed technique only the discrete sampled noise is considered. HSPICE simulator and analytical analysis are used to estimate the sampled noise specification on each clock state. Next, using difference equations of the circuit, time domain simulation is done by MATLAB. Based on this method, a SC integrator is analyzed and results compared to the measured noise response  

Sigma-Delta modulator ADCs used in signal processing applications usually, are implemented by switched-capacitor (SC) circuits and CMOS transmission gates due to its simplicity for implementation. Channel charge injection (CCI) and clock feed-through (CFT) are two major non-ideal effects existing in TG switches and SC integrators reducing modulator total SNR, its linearity and its total gain. This paper presents a precise model for SC integrator including CCI and CFT non-ideal effects in MATLAB SIMULINK environment which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) Sigma-Delta modulators. Evaluation and validation of extracted models were... 

Demand for more efficient energy storage devices stimulates efforts to search and develop new materials and composites with promising properties. In this regard, composite materials, including carbonaceous materials and metal oxides have attracted a great attention due to better electrochemical performance as compared to their single material analogues. For the first time, herein, we report a new and simple procedure for preparing porous highly oriented pyrolytic graphite/nickel hydroxide composite (P-HOPG/Ni(OH)2) via a fast and simple two-step electrochemical method including potentiostatic routes. In the first step, a low anodic potential (2 V) was applied to pristine HOPG in 0.5 M H2SO4... 

Optimal Reactive Power Dispatch (ORPD) has a salient impact on decreasing the power loss of transmission lines and adjusting the voltage deviation. The parameters that are used for the ORPD are tap settings of transformers, voltages of generating plants and the output of compensating device such as capacitor banks and synchronous condensors. In this paper settings of FACTS devices are considered as additional parameters in solving the ORPD problem. Also the genetic algorithm has been used to find the optimal settings of the controlling parameters. The results of the ORPD have been obtained on a 30 bus IEEE network. © 2009 IEEE  

In this paper, an optimized topology for switched-capacitor (SC) multilevel inverter is proposed. The proposed topology, which is referred to as Optimized Switched-Capacitor Multilevel Inverter (OSC-MI), offers a boosted staircase voltage by using only one dc source and fewer switches count. Since each industrial load requires a specific power factor (PF), an optimal converter can be designated in a way that it both satisfies the required PF and employs fewer switches and gate drivers. Therefore, the main strategy of reducing switches count in the proposed topology is to design the converter according to the required PF value. In this paper, the theoretical analytics and comparison results... 

In this paper, we have studied the effect of annealing under slightly oxidizing ambient (N2 + O2) on the structural and electrical characteristics of a limited number of silicon nanoparticles embedded in an ultra-thin SiO2 layer. These nanoparticles were synthesized by ultra-low energy (1 keV) ion implantation and annealing. Material characterization techniques including transmission electron microscopy (TEM), Fresnel imaging and spatially resolved electron energy loss spectroscopy (EELS) have been used to evaluate the effects of oxidation on structural characteristics of nanocrystal layer. Electrical transport characteristics have been measured on less than one hundred nanoparticles by... 

Drawing an accurate relationship between settling time and the power consumption of the amplifier is a challenging problem in Switch Capacitor circuits especially when it includes non-linear effects. In this paper, a new method for the estimation of this relationship including both non-linear settling as a result of slew-rate and small signal settling in the 3 rd order amplifier is proposed. The results show that the proposed settling time estimation is more accurate than other conventional methods when it is compared with the circuit level simulations. The proposed method has error smaller than 10% for the third order OpAmp in estimating settling error. This is about two times more accurate... 

A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply  

Artificial neural network was used to calculate the performance of a model supercapacitor as signified by the power density, energy density and utilization to the synthetic, intrinsic and operating characteristics. A four-layer neural net having two hidden layers having 6 and 15 nodes was found to be well capable of simulating the capacitor performance with the convergence achieved often a relatively small number of epochs. As for the input parameters, crystal size, surface lattice length, exchange current density of the capacitor active material and the cell current employed while utilization, energy density and power density were the outputs. © 2006 Elsevier B.V. All rights reserved  

In this paper, we present a study on the contribution of silicon nanocrystals to the electrical transport characteristics of large (100 μm × 100 μm) and small (100 nm × 100 nm) metaloxide-semiconductor (MOS) capacitors at room temperature. A layer of silicon nanocrystals is synthesized within the oxide of these capacitors by ultra-low energy ion implantation and annealing. Several features including negative differential resistance (NDR), sharp current peaks and random telegraph signal (RTS) are demonstrated in the current-voltage and current-time characteristics of these capacitors. These features have been associated to charge storage in silicon nanocrystals and to the resulting Coulomb...