Sharif Digital Repository

Several unicast and multicast routing protocols have been presented for MPSoCs. Multicast protocols in NoCs are used for cache coherency in distributed shared memory systems, replication, barrier synchronization, or clock synchronization. Unicast routing algorithms are not suitable for multicast, as they increase traffic, congestion and deadlock probability. Famous multicast schemes such as tree-based and path-based schemes have been proposed originally for multicomputers and recently adapted to NoCs. In this paper, we propose a switch tree-based multicast scheme, called STBA. This method supports tree construction with a minimum number of routers. Our evaluation results reveal that, for... 

We propose a solvable generalization of the Tonks-Girardeau model that describes a coherent one-dimensional (1D) gas of cold two-level bosons which interact with two external fields in a Ramsey interferometer. They also interact among themselves by idealized, infinitely strong contact potentials, with interchange of momentum and internal state. We study the corresponding Ramsey fringes and the quantum projection noise which, essentially unaffected by the interactions, remains that for ideal bosons. The dual system of this gas, an ideal gas of two-level fermions coupled by the interaction with the separated fields, produces the same fringes and noise fluctuations. The cases of time-separated... 

In this paper, we analyze and discuss the performance limits of optical clock recovery systems using a phase-locked loop (PLL) structure with nonlinear two-photon absorption (TPA) phase detection scheme. The motivation in analyzing the aforementioned optical PLL with TPA receiver structure is due to a recent successful experiment reported in [8]. We characterize the mathematical structure of PLLs with TPA, so as to evaluate the performance limits on optical clock recovery mechanism. More specifically, we identify two intrinsic sources of phase noise in the system namely, the ON-OFF nature of the incoming data pulses and the detector's shot noise that ultimately limit the performance of the... 

In this paper, Stochastic Activity Networks (SANs) are exploited to model and evaluate the power consumption and performance of virtualized servers in cloud computing. The proposed SAN models the physical servers in three different power consumption and provisioning delay modes, switching the status of the servers according to the workload of the corresponding cluster if required. The Dynamic Voltage and Frequency Scaling (DVFS) technique is considered in the proposed model for dynamically controlling the supply voltage and clock frequency of CPUs. Thus, Virtual Machines (VMs) on top a physical server can be divided into several power consumption and processing speed groups. According to the... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Abstract Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

In this study, we have used a single link system with a pair of muscles that are excited with alpha and gamma signals to achieve both point to point and oscillatory movements with variable amplitude and frequency. The system is highly nonlinear in all its physical and physiological attributes. The major physiological characteristics of this system are simultaneous activation of a pair of nonlinear musclelike- actuators for control purposes, existence of nonlinear spindle-like sensors and Golgi tendon organlike sensor, actions of gravity and external loading. Transmission delays are included in the afferent and efferent neural paths to account for a more accurate representation of the reflex... 

A systematic procedure of simulating charge pump based delay locked loops (DLLs) represents in this paper. The presented procedure is based on the systematic modeling of the DLL components in Matlab Simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented  

This study demonstrates the glucose-template assisted synthesis of hydrogen-treated Pt: TiO2/WO3 composites, and their round-the-clock photoactivity towards methanol (MeOH) degradation under light illumination and in dark. XRD indicated increasing rutile fraction in TiO2 as a function of template removal, WO3 crystallinity and H2 treatment process. The presence of oxygen vacancies in WO3 was confirmed by XPS. Lower recombination rate and higher surface area were observed in the optimized H2-Pt-G:TiO2/WO3 catalyst. The presence of oxygen vacancies and optical enhancements due to the synergistic interactions of the multi-system (TiO2, WO3 and Pt) extended the visible light absorption of the... 

A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 μm CMOS technology and operating in 10 Gbps... 

In high-speed analog-To-digital converters (ADCs), two main factors contribute to high power consumption. The first is the super linear relationship with the sampling rate; i.e., by doubling the sampling rate, the power consumption more than doubles. The second factor arises from the consumption of analog circuitry responsible to mitigate the jitter noise. By employing a multichannel sampling system, one can achieve high sampling rates by incorporating multiple low sampling-rate channels, which results in a linear scaling of power consumption with the number of channels. The main drawback of this system is the timing mismatch between the sampling channels. In this paper, we intend to jointly... 

Delay in communication wires causes design iterations in system-on-chip. Latency-insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling-based latency-insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm... 

In this paper, a wideband, circularly polarized patch antenna is proposed that leverages the unidirectional resonant modes of a circular patch mounted on top of a grounded dielectric-ferrite substrate. The proposed antenna is fed via the proximity coupling method and several parasitically coupled patches are placed on a dielectric superstrate to enhance the impedance bandwidth of the antenna. The resonant modes of the structure rotate only in the clockwise or counter clockwise directions. In the frequency range where the effective permeability of the ferrite layer is negative, the resonance frequencies of these modes differ significantly, which produces a large axial ratio (AR) bandwidth.... 

FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter, detection and correction is performed in predefined error-correction intervals. In both of them error detections and corrections of k-input LUTs are performed with a latency of 2k clock cycle without any... 

This study describes the synthesis of TiO2/WO3 composite systems with a varying concentration of WO3 by a glucose-template assisted method and demonstrates their round-the-clock photoactivity performance towards the degradation of methanol (MeOH) under illumination and dark conditions. XRD results indicated a biphasic anatase-rutile nature of TiO2, with tunable concentrations with respect to the WO3 loading. WO3 incorporation extended the light absorption of the system towards visible light, increasing the observed photoactivity. The obtained results were further validated using photo-electrochemical investigations such as photocurrent measurements and the impedance response of the systems.... 

Communication wire delay between multiple blocks is becoming a critical issue in System on Chip (SoC) design. Scheduling-based Latency-Insensitive Design (LID) is a method to alleviate wire delays by utilizing a central scheduling scheme for periodic clock gating of the blocks. The scheduling scheme resides in shift registers as sequences of '1' and '0' bits. In many systems, these sequences are too long, and have large area overhead. This problem indisposes the implementation of the scheduling based protocol. This paper proposes an algorithm that finds sequences with shorter lengths in comparison with the prior algorithm. On synthetic/random test cases, the algorithm gives 45% reduction on... 

This letter addresses the problem of joint localization and clock synchronization in distributed multiple-input multiple-output (MIMO) radar systems. While the well-known two-stage weighted least squares (WLS) method provides an acceptable estimate of target position when a rough approximation of antennas clock parameters, the drifts and offsets, is available, its performance can degrade quickly if the level of uncertainty in these values increases. The proposed method offers a solution for synchronizing the clocks while simultaneously improving the target position estimate. The uncertainty in positions of antennas is also taken into account. The presented method is shown to be approximately... 

In this paper, an algebraic solution for elliptic localization in multiple-input multiple-output (MIMO) radar systems is proposed by taking the uncertainties in antenna positions and their clock parameters into account. Through nonlinear transformation and multi-stage processing, the target position is estimated in closed-form by successively utilizing the weighted least squares estimator. Theoretical analysis demonstrates that the proposed method is able to attain the Cramer-Rao lower bound (CRLB) performance under mild Gaussian error. The conditions for achieving the CRLB are derived as well. The numerical simulations confirm the analytical results and demonstrate significant performance... 

Scaling of CMOS devices being aggressively decreasing by reduce of transistor dimensions. However, such level of integration leads to many physical limit and transistors cannot get much smaller than their current size. Quantum-dot Cellular Automate is a novel technology which significantly reduces physical limit of CMOS devices implementation, thus, it can be an appropriate candidate to be substituted for CMOS technology. In addition to high integration density of QCA circuits, other unique specifications such as high speed and low power consumption encourage researchers to utilize this technology instead of CMOS technology. In this paper, a new layout of XOR gate is presented in QCA...