Sharif Digital Repository

We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller circuitry to restore the system to the fault-free state. As a case study, we have implemented the proposed ScTMR technique on an embedded processor, suited for safety-critical applications. Exhaustive fault injection experiments reveal that the proposed architecture has the error detection and... 

The exact symbol and bit error probabilities of linearly modulated signals in frequency non-selective Rician fading channels with Lth diversity branches are derived, where coherent detection with maximum ratio combining (MRC) is used at the receiver. For performance evaluation, the multiplicative distortion is combined with the additive Gaussian noise and form an additive noise is formed. This method allows computing the exact symbol and bit error probabilities of M-ary phase shift keying (M-PSK), M-ary quadrature amplitude modulation (M-QAM), M-ary amplitude modulation (M-AM) and M-ary amplitude modulation phase modulation (M-AMPM) for any arbitrary bit mappings. The results contain several... 

While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is... 

A Multiplicative Patchwork Method (MPM) for audio watermarking is proposed in this paper. In order to embed watermark data within the host signal, two subsets of the host signal features are selected using two secret keys. Then, watermark data is inserted simply by multiplying one subset and leaving the other one unchanged. In order to have an error free detection in attack-free case, embedding is performed in the selected frames of the host signal which satisfies a certain condition. This method is implemented in the wavelet domain and approximation coefficients are used for data embedding. Furthermore, the inaudibility of watermark insertion is controlled using iterative approach aided by... 

Inserting redundancy to arithmetic codes is a common strategy to add error detection capability to this well-known family of source codes. By using this strategy error correction is possible through some decoding algorithms such as Viterbi decoder. In this paper a system has proposed that uses finite state integer arithmetic codes (FSAC) as a joint source-channel code in combination with a cyclic redundancy check (CRC) and a List Viterbi decoder. The proposed scheme has shown better performance than previous ones. © 2009 IEEE  

In this paper, a high speed and low cost error correction technique is proposed for the Carry Select Adder (CSA) which can correct both transient and permanent errors and is applicable on all partitioning types of the basic CSA circuit. The proposed error correction technique is compatible with all existing error detection techniques which are proposed for the CSA adder. The synthesized results show that applying this novel error correction technique to a CSA with error detection technique results in up to 18.4%, 3.1% and 14.9%, increase in power consumption, delay and area respectively. © 2009 IEEE  

This paper presents a Multiplicative Patchwork Method (MPM) for audio watermarking. The watermark signal is embedded by selecting two subsets of the host signal features and modifying one subset multiplicatively regarding the watermark data, whereas another subset is left unchanged. The method is implemented in wavelet domain and approximation coefficients are used to embed data. In order to have an error-free detection, the watermark data is inserted only in the frames where the ratio of the energy of subsets is between two predefined values. Also in order to control the inaudibility of watermark insertion, we use an iterative algorithm to reach a desired quality for the watermarked audio... 

This paper presents a novel method for cooperative educational dissemination systems. Taking into consideration the inherent characteristics of distance learning video streams (existence of a few slow moving objects in a classroom), we have proposed a novel content-based video coding method that is very efficient at low bitrate channels. On the encoding side, we have applied a background subtraction algorithm for motion segmentation using a novel statistical background modeling approach. At each frame, the moving objects are extrapolated with a rectangular model and tracked frame by frame (which forms the only data needed to be sent over the channel). On the decoding side, we have used a new... 

This paper proposes a new technique called CFEDC to detect and correct control flow errors (CFEs) without program interruption. The proposed technique is based on the modification of application software and minor changes in the underlying hardware. To demonstrate the effectiveness of CFEDC, it has been implemented on an OpenRISC 1200 as a case study. Analytical results for three workload programs show that this technique detects all CFEs and corrects on average about 81.6% of CFEs. These figures are achieved with zero error detection /correction latency. According to the experimental results, the overheads are generally low as compared to other techniques; the performance overhead and the... 

This paper proposes a Distant Speech Recognition system based on a novel speaker Localization and Beamforming (SRLB) algorithm. To localize the speaker an algorithm based on Steered Response Power by utilizing harmonic structures of speech signal is proposed. This new scheme has the ability of speaker verification by fundamental frequency variation: therefore it can be utilized in the design of a speech recognition system for verified speakers. Then the performance of the Farsi speech recognition engine is evaluated under notorious conditions of noise and reverberation. Simulation results and tests on real data shows that by utilizing proposed localization scheme, recognition accuracy... 

The increasing rate of transient faults necessitates the use of on-chip fault-tolerant techniques in embedded microprocessors. Performance overhead is a challenging problem in on-chip fault-tolerant techniques used in the random logic of the embedded microprocessors. This paper presents a signature-based error detection and roll-back recovery technique for the control logic with much lower performance overhead as compared to many previous techniques. The low performance overhead is achieved by eliminating the fault masking overhead cycles in the previous techniques. The performance overhead is analytically studied, and the analytical results recommend at which fault rate the use of the... 

This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This Scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and in the target addresses of branch instructions which lead to erroneous branches. The second mechanism uses signature monitoring to detect errors occurring in the sequential instructions. The scheme is implemented using a watchdog processor for an VHDL model of the LEON2 processor. About 31800 simulation faults were injected into the LEON2 processor. The results show that the error detection coverage is about 99.5% with average detection... 

Reliability and low power consumption are two major design objectives in today's embedded systems. Since floating-point units (FPU) are required for some embedded applications (e.g., multimedia applications), careful considerations should be given to the reliability and power consumptions of FPUs used in embedded systems. When using existing fault handling mechanisms for FPUs, it has been observed that the division operation imposes a considerable hardware overhead as compared to the addition, subtraction, and multiplication operations. Although the division operation is less frequently used, in reliable applications it is a must that all the components operate properly. In this paper, we... 

Any clutter edge in the reference window of a radar CFAR detection, produces an error in the clutter power estimation which reduces the detectability of the cell under test (CUT). In processors such as OS-CFAR, the designers have attempted to improve the detection performance, nevertheless, none of these processors applies an intelligent method of clutter edge recognition and destroyer data elimination. Therefore any of these processors are effective in some especial cases of nonhomogeneous environment, but are deficient in other cases. In this paper an intelligent method is proposed for clutter edge recognition. This method determines the borders in which the clutter statistics are changing... 

In this paper, an iterative signal reconstruction method is extended to cancel multi-user clipping noise in a uplink MC-CDMA systems. Clipping is the simplest method to overcome high peak-to-average power ratio of multi-carrier signals but it makes the multi-carrier signals distorted. Reconstruction methods use non-distorted samples to reconstruct distorted samples in the receiver but multi-user interference causes the methods do not work properly because all the received samples are distorted by clipping and interference and so there is no undistorted samples to be used in recovering clipped samples. On the other hand, multi-user interference cancellation methods do not work properly... 

In this study, we presented a method for distributing data storage by using residue number system for mobile systems and wireless networks based on peer to peer paradigm. Generally, redundant residue number system is capable in error detection and correction. In proposed method, we made a new system by mixing Redundant Residue Number System (RRNS), Multi Level Residue Number System (ML RNS) and Multiple Valued Logic (MVL RNS) which was perfect for parallel, carry free, high speed arithmetic and the system supports secure data communication. In addition it had ability of error detection and correction. In comparison to other number systems, it had many improvements in data security, error... 

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer... 

OFDM is a multicarrier modulation scheme with high bandwidth efficiency and robustness to multipath environment used in high data rate transmission. However, a drawback of this system is the large Peak-to-Average-Power Ratio (PAR) of the transmit signal which makes its straightforward implementation quite costly. PAR in an OFDM based system can be reduced significantly by PTS method for which data recovery requires side information (SI) about the phases used at transmitter. Sending SI, not only reduces the rate, but also increases BER, for any error in SI detection can damage a large amount of transmitted information. By introducing a new phase set, we propose a PTS based method for MPSK... 

SRAM cache memories suffer from single event upset (SEU) faults induced by energetic particles such as neutron and alpha particles. To protect these caches, designers often use error detection and correction codes, which typically provide single-bit error detection and even correction. However, these codes have low error detection capability or incur significant performance penalties. In this paper, a protected cache scheme based on the variable associativity of sets is presented. In this scheme, cache space is divided into sets of different sizes with variable tag field lengths. The other remained bits of tags are used for protecting the tag using a new protection code. This leads to... 

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 μm CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of...