Sharif Digital Repository

In large systems, economical and efficiency concerns restrict the allocation of each resource to every node in the network. Therefore, it is desirable to distribute copies of resource in order to share them and achieve a certain performance measure. In this paper, we consider the problem of distributing resources in Cube-Connected Cycles. Both adjacency and distant placements are considered in this paper. In adjacency placements, dominating sets and perfect dominating sets are used. The proposed algorithms for distant placements use known placements for basic hypercube graphs. Therefore, in these placements we avoid the additional costs needed for deploying the network. We prove that the... 

In a large system, it is neither economical nor efficient to equip each node with a copy of the resource, and it is desirable to distribute the copies of the resource so that certain performance measure is obtained. In this paper we consider the problem of distributing resources in the edge product of networks. The algorithms presented in this paper make use of the known placements for the basic graphs composing the product graph. Therefore, in these placements we avoid the additional costs needed for deploying and rescaling the network. © 2008 IEEE  

The WK-recursive mesh and WK-pyramid networks are recursively-defined hierarchical interconnection networks with excellent properties which well idealize them as alternatives for mesh and traditional pyramid interconnection topologies. They have received much attention due to their favorable attributes such as small diameter, large connectivity, and high degree of scalability and expandability. In this paper, we deal with packagibility and layout area of these networks. These properties are of great importance in the implementation of interconnection networks on chips. We show that WK-recursive, mesh-pyramid and WK-pyramid networks can be laid out in an area of O(N2) which is the optimal... 

The planar-adaptive routing algorithm is a simple method to enhance wormhole routing algorithms for fault-tolerance in meshes but it cannot handle faults on the boundaries of mesh without excessive loss of performance. In this paper, we show that this algorithm can further be improved using a flag bit introduced for guiding misrouted messages. So, the proposed algorithm can be used to route messages when fault regions touch the boundaries of the mesh. We also show that our scheme does not lead to diminish the performance of the network and only three virtual channels per physical channels are sufficient for tolerating multiple boundary faulty regions. © 2008 Springer-Verlag Berlin Heidelberg... 

The Network-on-Chip (NoC) paradigm brings networks inside chips. We use the routing capabilities inside NoC to serve as a replacement for Virtual Method Table (VMT) for Object-Oriented (OO) designed hardware/software co-design systems where some methods could be implemented as hardware modules. This eliminates VMT area and performance overhead in OO co-designed embedded systems where resources are limited and where some functionality needs to be implemented in hardware to meet performance goals of the system. Our experimental results on real world embedded applications show up to 32.15% lower area and up to 5.1% higher speed compared to traditional implementation using VMT. © 2007 Elsevier... 

The surface area which is defined as the number of vertices at a given distance from a base vertex of a graph is considered to be as one of the most useful yet abstract combinatorial properties of a graph. The applicability of surface area spans many problem spaces such as those in parallel and distributed computing. These problems normally involve combinatorial analysis of underlying graph structures (e.g., spanning tree construction, minimum broadcast algorithms, efficient VLSI layout, performance modeling). In this paper, we focus on the problem of finding the surface area of a class of popular graphs, namely the family of WK-recursive and swapped networks. These are attractive networks... 

The Pyramid network is a desirable network topology used as both software data-structure and hardware architecture. In this paper, we propose a general definition for a class of pyramid networks that are based on grid connections between the nodes in each level. Contrary to the conventional pyramid network in which the nodes in each level form a mesh, the connections between these nodes may also be according to other grid-based topologies such as the torus, hypermesh or WK-recursive. Such pyramid networks form a wide class of interconnection networks that possess rich topological properties. We study a number of important properties of these topologies for general-purpose parallel processing... 

The ever-expanding growth of internet traffic enforces deployment of massive Data Center Networks (DCNs) supporting high performance communications. Optical switching is being studied as a promising approach to fulfill the surging requirements of large scale data centers. The tree-based optical topology limits the scalability of the interconnected network due to the limitations in the port count of optical switches and the lack of optical buffers. Alternatively, buffer-less Fast Optical Switch (FOS) was proposed to realize the nanosecond switching of optical DCNs. Although FOSs provide nanosecond optical switching, they still suffer from port count limitations to scale the DCN. To address... 

In this paper, jitter due to both capacitive and inductive coupling is studied. Maximum frequency of driving signal on a wire is limited by its input rise time, fall time, pulse width, and the coupling effect from its neighbors. The analytical expressions to estimate the deterministic jitter time due to these effects are presented. The estimation is based on the fastest and slowest approximation of the signal waveform components. Also, we have extracted the eye opening parameters of the eye diagram. The inductance effects significance is shown on eye opening and jitter time. The 45nm technology is used for estimating the horizontal and vertical eye opening and jitter time. The presented... 

The application of digital technologies in power systems has resulted in an evolutionary replacement of electromechanical devices with numerical ones featuring internal digital processors with communication capabilities. A substation automation system (SAS) deploys substation operation functions, including control, protection, monitoring, and measuring. Ethernet technology and local area networks (LANs) make it possible to design substation communication architectures with greater reliability, availability, speed, and cost savings than conventional hard-wired systems. This paper proposes a new method to describe topologies of the SAS as an interconnected network. The concept of data... 

The demand for robust computation systems has led to the increment of the number of processing cores in current chips. As the number of processing cores increases, current electrical communication means can introduce serious challenges in system performance due to the restrictions in power consumption and communication bandwidth. Contemporary progresses in silicon nano-photonic technology have provided a suitable platform for constructing photonic communication links as an alternative for overcoming such problems. Topology is one of the most significant characteristics of photonic interconnection networks. In this paper, we have introduced a novel topology, aiming to reduce insertion loss in... 

This paper presents a general methodology for generating deadlock-free routing algorithms for irregular networks. Constructing a spanning tree on the given network, assigning directions to the network channels, creating deadlock-free zones, and specifying a logical sequence of the produced deadlock-free zones are the four fundamental steps that the proposed methodology takes to generate deadlock-free and connected routing algorithms. By applying the proposed methodology with two known labeling methods we have generated six irregular routing algorithms: three of them are novel routing algorithms and three of them (the Up/Down, Left/Right, and L-turn routing algorithms) have already been... 

On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space exploration and finding the best NoC solution for each specific application, a fast and flexible NoC simulator is necessary, especially for large design spaces. In this paper, we present an FPGA-based NoC co-simulator, which is able to be configured via software. In our proposed NoC simulator, entitled DuCNoC, we implement a Dual-Clock router micro-architecture, which demonstrates 75x-350x speed-up against BOOKSIM.... 

In this paper, we present a comprehensive analysis of the impact of aging on the interconnection network of field-programmable gate arrays (FPGAs) and propose novel approaches to mitigate the aging effects on the routing network. We first show the insignificant impact of aging on data integrity of FPGAs, i.e., static noise margin and soft error rate of the configuration cells, as well as we show the negligible impact of the mentioned degradations on the FPGA performance. As such, we focus on the performance degradation of datapath transistors. In this regard, we propose a routing accompanied by a placement algorithm that prevents constant stress on transistors by evenly distributing the... 

A routing algorithm defines a route which packet traverses to get to destination. In this research we study some kind of routing algorithms that are used in internal connections networks of multi-processor and multi-computers systems. Then we discuss about some routing algorithms which have been implemented network on chip architecture. First, we present a group of routing algorithms based on various criterions, and review so-called category. Afterwards, we study adaptive and deterministic routing algorithms and express circular model applying in internal connections networks and its governing rules in order to prevent dead lock. Then we survey adaptive algorithms such as Deflection routing,... 

This paper probes the impact of utilizing an IPFC on the reliability indices of interconnected power systems. First, a concise presentation of IPFC and its structure are provided and the reliability model of two unequally-rated parallel transmission lines equipped with IPFC is then extracted. The assumed IPFC is composed from two parallel converting bridges associated with each line. Afterwards, based-on equivalent assisting unit approach, different commonly-used adequacy indices including the loss of load expectation (LOLE), loss of energy expectation (LOEE) and system minutes (SM) are calculated. A set of numerical analyses are conducted to illustrate the sensitivity of these indices with... 

The WK-recursive mesh and WK-pyramid networks are recursively defined hierarchical interconnection networks with excellent properties which well idealize them as alternatives for mesh and traditional pyramid interconnection topologies. They have received much attention due to their favorable attributes such as small diameter, large connectivity, and high degree of scalability and expandability. In this paper, we deal with pancyclicity and surface area of these networks. These properties are of great importance in the implementation of a variety of parallel algorithms in multicomputers. We show that WK-recursive mesh network is 1-partially pancyclic, i.e. any cycle of length 3, 4, 6,..., and... 

We propose a partially adaptive fault-tolerant and deadlock-free routing algorithm in n-dimensional meshes based on the fault-tolerant planar-adaptive routing and Duato's protocol. In particular, we show that only four virtual channels per physical channel are sufficient for tolerating multiple faulty regions even in the case of n-dimensional meshes. Our scheme is able to handle faulty blocks whose associated fault rings have overlaps. In addition, it can be used to route messages when fault regions touch the boundaries of the mesh. A flag bit is introduced for guiding misrouted messages. Messages are routed adaptively in healthy regions of the network. Once a message faces a faulty region,...